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1.发明申请METHODS FOR DICING A COMPOUND SEMICONDUCTOR WAFER, AND DICED WAFERS AND DIE OBTAINED THEREBY 有权化合物半导体晶片的方法，以及由其获得的衍射波形公开(公告)号：US20140217556A1
公开(公告)日：2014-08-07
申请号：US13758265
申请日：2013-02-04
发明人： Chee Siong Peh , Chiew Hai NG , David G. McIntyre
IPC分类号： H01L23/544 , H01L21/50
CPC分类号： H01L23/544 , H01L21/302 , H01L21/30621 , H01L21/50 , H01L21/6836 , H01L21/78 , H01L25/042 , H01L25/167 , H01L31/02325 , H01L31/02327 , H01L31/18 , H01L2221/68336 , H01L2924/0002 , H01S5/0203 , H01S5/02268 , H01S5/4087 , H01S5/423 , Y10S438/975 , H01L2924/00
摘要： Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.
摘要翻译： 提供了使用掩模技术和等离子体蚀刻技术将化合物半导体晶片切割成模具的方法。 使用这些方法可以获得具有平滑侧壁，各种形状和尺寸以及各种侧壁型材的复合半导体管芯。 另外，通过使用这些技术来执行切割操作，可以确定地确定模具相对于侧壁的特征的位置，使得一个或多个侧壁可以用作被动对准特征以精确对准一个 或更多的模具与外部设备。
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公开(公告)号：US09851516B2
公开(公告)日：2017-12-26
申请号：US14926250
申请日：2015-10-29
发明人： Chee Siong Peh , Chiew Hai Ng , David Graham McIntyre , Tom White
IPC分类号： G02B6/42
CPC分类号： G02B6/4231 , G02B6/4204 , G02B6/4207 , G02B6/4212 , G02B6/428
摘要： A system, optical assembly, and optical communication system are disclosed. The optical assembly is disclosed as including an optoelectronic component having a predetermined shape and an optical module that permits light emitted by the optoelectronic component or travelling to the optoelectronic component to pass therethough. The optical module is further disclosed as including a first surface and an opposing second surface, the first surface of the optical module including a first mating feature to receive the optoelectronic component, and the second surface of the optical module including a receptacle to receive and align an optical fiber with the optoelectronic component.
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3.发明授权Systems and methods for plasma etching compound semiconductor (CS) dies and passively aligning the dies 有权用于等离子体蚀刻化合物半导体（CS）的系统和方法模具并被动地对准模具公开(公告)号：US09034734B2
公开(公告)日：2015-05-19
申请号：US13758265
申请日：2013-02-04
发明人： Chee Siong Peh , Chiew Hai Ng , David G. McIntyre
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301 , H01L21/44 , H01L21/48 , H01L21/50 , H01L21/76 , H01L21/30 , H01L23/544 , H01L21/302 , H01L21/683
CPC分类号： H01L23/544 , H01L21/302 , H01L21/30621 , H01L21/50 , H01L21/6836 , H01L21/78 , H01L25/042 , H01L25/167 , H01L31/02325 , H01L31/02327 , H01L31/18 , H01L2221/68336 , H01L2924/0002 , H01S5/0203 , H01S5/02268 , H01S5/4087 , H01S5/423 , Y10S438/975 , H01L2924/00
摘要： Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.
摘要翻译： 提供了使用掩模技术和等离子体蚀刻技术将化合物半导体晶片切割成模具的方法。 使用这些方法可以获得具有平滑侧壁，各种形状和尺寸以及各种侧壁型材的复合半导体管芯。 另外，通过使用这些技术来执行切割操作，可以确定地确定模具相对于侧壁的特征的位置，使得一个或多个侧壁可以用作被动对准特征以精确对准一个 或更多的模具与外部设备。
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4.发明申请METHODS FOR DICING A COMPOUND SEMICONDUCTOR WAFER, AND DICED WAFERS AND DIE OBTAINED THEREBY 审中-公开化合物半导体晶片的方法，以及由其获得的衍射波形公开(公告)号：US20150098482A1
公开(公告)日：2015-04-09
申请号：US14572371
申请日：2014-12-16
发明人： Chee Siong Peh , Chiew Hai NG , David G. McIntyre
IPC分类号： H01L25/16 , H01S5/40 , H01S5/02 , H01L25/04 , H01L31/0232
CPC分类号： H01L23/544 , H01L21/302 , H01L21/30621 , H01L21/50 , H01L21/6836 , H01L21/78 , H01L25/042 , H01L25/167 , H01L31/02325 , H01L31/02327 , H01L31/18 , H01L2221/68336 , H01L2924/0002 , H01S5/0203 , H01S5/02268 , H01S5/4087 , H01S5/423 , Y10S438/975 , H01L2924/00
摘要： Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.
摘要翻译： 提供了使用掩模技术和等离子体蚀刻技术将化合物半导体晶片切割成模具的方法。 使用这些方法可以获得具有平滑侧壁，各种形状和尺寸以及各种侧壁型材的复合半导体管芯。 另外，通过使用这些技术来执行切割操作，可以确定地确定模具相对于侧壁的特征的位置，使得一个或多个侧壁可以用作被动对准特征以精确对准一个 或更多的模具与外部设备。
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公开(公告)号：US20170123169A1
公开(公告)日：2017-05-04
申请号：US14926250
申请日：2015-10-29
发明人： Chee Siong Peh , Chiew Hai Ng , David Graham McIntyre , Tom White
CPC分类号： G02B6/4231 , G02B6/4204 , G02B6/4207 , G02B6/4212 , G02B6/428
摘要： A system, optical assembly, and optical communication system are disclosed. The optical assembly is disclosed as including an optoelectronic component having a predetermined shape and an optical module that permits light emitted by the optoelectronic component or travelling to the optoelectronic component to pass therethough. The optical module is further disclosed as including a first surface and an opposing second surface, the first surface of the optical module including a first mating feature to receive the optoelectronic component, and the second surface of the optical module including a receptacle to receive and align an optical fiber with the optoelectronic component.
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公开(公告)号：US20160226223A1
公开(公告)日：2016-08-04
申请号：US14610161
申请日：2015-01-30
CPC分类号： H01S5/423 , G02B6/4214 , G02B6/4249 , H01S5/0425
摘要： Various VCSEL device packages and VCSEL array configurations are disclosed. In one example, a device contains two or more VCSELs, each VCSEL having a substantially triangular body. Such device packages allow for denser VCSEL array configurations than those provided by traditional VCSEL device packages. The denser VCSEL array configurations not only allow for more VCSELs to be batch manufactured per wafer but also allow for denser layouts on various mounting surfaces.
摘要翻译： 公开了各种VCSEL器件封装和VCSEL阵列配置。 在一个示例中，设备包含两个或更多个VCSEL，每个VCSEL具有基本上三角形的主体。 这样的器件封装允许比传统VCSEL器件封装提供的更多的VCSEL阵列配置。 更致密的VCSEL阵列配置不仅允许每个晶片批量生产更多的VCSEL，而且允许在各种安装表面上的更密集的布局。
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