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公开(公告)号：US11989143B2
公开(公告)日：2024-05-21
申请号：US17809465
申请日：2022-06-28
Inventor： Shreyas Shah , George Apostol, Jr. , Nagarajan Subramaniyan , Jack Regula , Jeffrey S. Earl
IPC: G06F13/16 , G06F12/06 , G06F12/08 , G06F12/0815 , G06F12/0837 , G06F12/0862 , G06F12/0868 , G06F12/14 , G06F13/40 , G06F13/42 , G06N20/00
CPC classification number: G06F13/1668 , G06F12/0646 , G06F12/0815 , G06F12/0837 , G06F12/0862 , G06F12/0868 , G06F12/1466 , G06F13/1642 , G06F13/1673 , G06F13/4022 , G06F13/4221 , G06F2213/0026 , G06N20/00
Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.
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公开(公告)号：US11947472B2
公开(公告)日：2024-04-02
申请号：US17809510
申请日：2022-06-28
Inventor： Shreyas Shah , George Apostol, Jr. , Nagarajan Subramaniyan , Jack Regula , Jeffrey S. Earl
IPC: G06F13/16 , G06F12/06 , G06F12/0815 , G06F12/0837 , G06F12/0862 , G06F12/0868 , G06F12/14 , G06F13/40 , G06F13/42 , G06N20/00
CPC classification number: G06F13/1668 , G06F12/0646 , G06F12/0815 , G06F12/0837 , G06F12/0862 , G06F12/0868 , G06F12/1466 , G06F13/1642 , G06F13/1673 , G06F13/4022 , G06F13/4221 , G06F2213/0026 , G06N20/00
Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.
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3.发明公开公开(公告)号：US20240220427A1
公开(公告)日：2024-07-04
申请号：US18605301
申请日：2024-03-14
Inventor： Shreyas Shah , George Apostol, JR. , Nagarajan Subramaniyan , Jack Regula , Jeffrey S. Earl
IPC: G06F13/16 , G06F12/06 , G06F12/0815 , G06F12/0837 , G06F12/0862 , G06F12/0868 , G06F12/14 , G06F13/40 , G06F13/42 , G06N20/00
CPC classification number: G06F13/1668 , G06F12/0646 , G06F12/0815 , G06F12/0837 , G06F12/0862 , G06F12/0868 , G06F12/1466 , G06F13/1642 , G06F13/1673 , G06F13/4022 , G06F13/4221 , G06F2213/0026 , G06N20/00
Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.
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