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公开(公告)号：US20090085789A1
公开(公告)日：2009-04-02
申请号：US12187632
申请日：2008-08-07
申请人： Axel Schuur , David H. Shen , Ann P. Shen
发明人： Axel Schuur , David H. Shen , Ann P. Shen
摘要： An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.
摘要翻译： 诸如CT SD-ADC的ADC包括产生充电和放电时钟信号的时钟产生电路，使得ADC中积分器的稳定时间增加。 时钟信号可以控制CT SD-ADC中的反馈SD-DAC。 时钟信号也可以是不对称的和/或可以导致积分器的建立时间大于系统时钟的一半。
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公开(公告)号：US20090088110A1
公开(公告)日：2009-04-02
申请号：US12236888
申请日：2008-09-24
申请人： Axel Schuur , Nianwei Xing , David H. Shen , Chien-Meen Hwang , Ann P. Shen , Niranjan Talwalkar
发明人： Axel Schuur , Nianwei Xing , David H. Shen , Chien-Meen Hwang , Ann P. Shen , Niranjan Talwalkar
IPC分类号： H04B1/16
摘要： A radio frequency receiver includes a passive mixer configured to receive and RF signal and a low input impedance circuit configured to receive the output of the passive mixer.
摘要翻译： 射频接收机包括被配置为接收RF信号的无源混频器和被配置为接收无源混频器的输出的低输入阻抗电路。
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公开(公告)号：US07639088B2
公开(公告)日：2009-12-29
申请号：US12110048
申请日：2008-04-25
申请人： David H. Shen , Ann P. Shen , Axel Schuur
发明人： David H. Shen , Ann P. Shen , Axel Schuur
摘要： Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.
摘要翻译： 实现功能用于锁相环（PLL）的系统和技术。 在一些方面，实现特征在于具有包括振荡器和可编程参考分频器电路或可编程反馈分频器电路的PLL电路的系统。 PLL包括控制电路，以通过将分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中来减少PLL建立时间所需的时间，以使振荡器在系统工作频率范围之外操作 在PLL操作启动期间振荡器。 在可变振荡器稳定之后，控制电路可以将另一个分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中。
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公开(公告)号：US20090085622A1
公开(公告)日：2009-04-02
申请号：US12110048
申请日：2008-04-25
申请人： David H. Shen , Ann P. Shen , Axel Schuur
发明人： David H. Shen , Ann P. Shen , Axel Schuur
IPC分类号： H03L7/06
摘要： Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.
摘要翻译： 实现功能用于锁相环（PLL）的系统和技术。 在一些方面，实现特征在于具有包括振荡器和可编程参考分频器电路或可编程反馈分频器电路的PLL电路的系统。 PLL包括控制电路，以通过将分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中来减少PLL建立时间所需的时间，以使振荡器在系统工作频率范围之外操作 在PLL操作启动期间振荡器。 在可变振荡器稳定之后，控制电路可以将另一个分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中。
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公开(公告)号：US20100329157A1
公开(公告)日：2010-12-30
申请号：US12495064
申请日：2009-06-30
申请人： Nianwei Xing , David H. Shen , Axel Schuur , Ann P. Shen
发明人： Nianwei Xing , David H. Shen , Axel Schuur , Ann P. Shen
CPC分类号： H03F3/45183 , H03F1/3211 , H03F2203/45342
摘要： Circuits and methods for a differential circuit involve having one of more pairs of differential transistors with back-gate terminals, where each of the back-gate terminals is biased by a tunable back-gate voltage to compensate for circuit mismatches in the differential circuit and reduce or eliminate even-order harmonics in the output signal. A compensation circuit can be configured to receive data relating to the differential output signal of the differential circuit, and to supply one or more back-gate voltages to the back-gate terminals of the differential transistors to adjust threshold voltages of the differential transistors and suppress even-order harmonics in the differential output signal of the differential circuit.
摘要翻译： 用于差分电路的电路和方法涉及具有多对具有背栅极端子的差分晶体管中的一个，其中每个背栅极端子被可调谐的栅极电压偏置以补偿差分电路中的电路不匹配并且减小 或消除输出信号中的偶次谐波。 补偿电路可以被配置为接收与差分电路的差分输出信号相关的数据，并且向差分晶体管的背栅极端子提供一个或多个反向栅极电压，以调整差分晶体管的阈值电压并抑制 差分电路的差分输出信号中的偶次谐波。
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公开(公告)号：US07646325B2
公开(公告)日：2010-01-12
申请号：US12187632
申请日：2008-08-07
申请人： Axel Schuur , David H. Shen , Ann P. Shen
发明人： Axel Schuur , David H. Shen , Ann P. Shen
IPC分类号： H03M1/12
摘要： An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.
摘要翻译： 诸如CT SD-ADC的ADC包括产生充电和放电时钟信号的时钟产生电路，使得ADC中积分器的稳定时间增加。 时钟信号可以控制CT SD-ADC中的反馈SD-DAC。 时钟信号也可以是不对称的和/或可以导致积分器的建立时间大于系统时钟的一半。
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公开(公告)号：US20090085671A1
公开(公告)日：2009-04-02
申请号：US12236344
申请日：2008-09-23
申请人： David H. Shen , James Burnham , Ali Tabatabaei , Ann P. Shen
发明人： David H. Shen , James Burnham , Ali Tabatabaei , Ann P. Shen
CPC分类号： H03F3/45183 , H03F3/193 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2203/45386 , H03F2203/45396 , H03F2203/45638 , H03F2203/7209
摘要： Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.
摘要翻译： 共享一个或多个负载电感器包括在第一放大器的第一端接收第一输入信号，并使用第一放大器放大第一输入信号。 第一放大器耦合到第一放大器的第二端处的一个或多个负载电感器，并且耦合到第一放大器的第三端处的一个或多个专用源电感器。 此外，在第二放大器的第一端处接收第二输入信号，该第二放大器使用第二放大器放大第二输入信号。 第二放大器耦合到第二放大器的第二端处的一个或多个负载电感器，并且耦合到第二放大器的第三端处的一个或多个专用源电感器。
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公开(公告)号：US20090085545A1
公开(公告)日：2009-04-02
申请号：US12175316
申请日：2008-07-17
申请人： David H. Shen , Ann P. Shen
发明人： David H. Shen , Ann P. Shen
IPC分类号： G05F1/565
CPC分类号： G05F1/565
摘要： In some implementations, a system includes a low-power voltage regulator that can switch between three power modes: a power shutdown mode, a low power mode, and a higher power mode. The system includes a selector coupled to the voltage regulator to switch between the low power mode and the higher power mode, and a switch to switch between the power shutdown mode and the low or higher power mode. The system also has a control circuit to control the switch and the selector to control operation of the voltage regulator in any of the three power modes. A total current used in the voltage regulator in the low power mode is on the order of microamps or nanoamps. The voltage regulator in the low power mode has two to more orders of magnitude of lower current use than the voltage regulator in the higher power mode.
摘要翻译： 在一些实施方式中，系统包括能够在三种功率模式之间切换的低功率稳压器：电源关闭模式，低功率模式和较高功率模式。 该系统包括耦合到电压调节器以在低功率模式和较高功率模式之间切换的选择器，以及在功率关断模式和低功率或更高功率模式之间切换的开关。 该系统还具有控制电路，用于控制开关和选择器，以控制三种功率模式中的任何一种电压调节器的工作。 在低功率模式下，电压调节器中使用的总电流为微安或纳秒级。 低功耗模式下的电压调节器在较高功率模式下具有比电压调节器低两到几个数量级的低电流使用。
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公开(公告)号：US07299020B2
公开(公告)日：2007-11-20
申请号：US10729674
申请日：2003-12-05
申请人： David H. Shen , Ann P. Shen
发明人： David H. Shen , Ann P. Shen
IPC分类号： H04B1/18
摘要： A multiple frequency RF communications receiver is disclosed which permits greater integration on standard silicon chips and consumes less power than previous receivers. A new method for selecting the various frequency bands with a high amount of isolation and low power consumption is described. Compared to previous receiver implementations, there is no loss of selectivity in the receiver.
摘要翻译： 公开了一种多频RF通信接收机，其允许在标准硅芯片上的更大集成并且消耗比先前的接收机更少的功率。 描述了一种用于选择具有大量隔离和低功耗的各种频带的新方法。 与以前的接收机实现相比，接收机中没有选择性的损失。
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公开(公告)号：US07532079B2
公开(公告)日：2009-05-12
申请号：US11764701
申请日：2007-06-18
申请人： David H. Shen , Ann P. Shen
发明人： David H. Shen , Ann P. Shen
IPC分类号： H03B5/00
CPC分类号： H03B5/366 , H03B2201/0208 , H03J2200/10
摘要： Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator.
摘要翻译： 实施例用于数字调谐晶体振荡器电路的技术和系统。 在一个方面，实施例的特征在于制造数字调谐晶体振荡器电路的方法。 该方法包括将多位输入信号接收到数字调制器中，通过过采样或通过噪声整形和过采样来调制具有数字调制器的多位输入信号，以产生具有比多数位更低位数的数字调制输出信号 位输入信号。 该方法还涉及将调谐电容器与晶体振荡器电路耦合，并将数字调制输出信号从数字调制器耦合到晶体振荡器电路和调谐电容器。 在一些实施例中，数字调制器可以是Δ-Σ调制器，噪声调制器，Δ调制器，脉冲宽度调制器，差分调制器或连续斜率增量调制器。
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