公开(公告)号：US20150340455A1

公开(公告)日：2015-11-26

申请号：US14376028

申请日：2013-11-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng CAO ,  Qi YAO ,  Luke DING ,  Bing SUN ,  Xiangchun KONG

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  H01L29/49 ,  G02F1/1368 ,  H01L27/12

CPC classification number: H01L29/42364 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2029/42388

Abstract: The present invention provides a thin film transistor and a method of fabricating the thin film transistor, an array substrate and a method of fabricating the array substrate, and a display device. The thin film transistor includes a substrate and a gate, an insulation layer, an active layer, a source and a drain which are provided on the substrate. A spacer layer is also provided between the gate and the active layer, and the spacer layer overlaps at least with one of the gate and the active layer having a smaller area in an orthographic projection direction. The spacer layer can effectively prevent material forming the gate from being diffused into the active layer, thereby ensuring stability of performance of the thin film transistor. In the array substrate utilizing the thin film transistor, the spacer layer further extends to a region corresponding to a gate line.

Abstract translation: 本发明提供一种薄膜晶体管和制造薄膜晶体管的方法，阵列基板和制造阵列基板的方法以及显示装置。 薄膜晶体管包括设置在基板上的基板和栅极，绝缘层，有源层，源极和漏极。 间隔层还设置在栅极和有源层之间，并且间隔层至少与栅极和有源层中的一个重叠，在正投影方向上具有较小的面积。 间隔层可以有效地防止形成栅极的材料扩散到有源层中，从而确保薄膜晶体管的性能的稳定性。 在利用薄膜晶体管的阵列基板中，间隔层进一步延伸到对应于栅极线的区域。

公开(公告)号：US20150357239A1

公开(公告)日：2015-12-10

申请号：US14513324

申请日：2014-10-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shi SHU ,  Zhijun LV ,  Jingxia GU ,  Yue SHI ,  Fangzhen ZHANG ,  Bing SUN ,  Chuanxiang XU

IPC: H01L21/768 ,  H01L21/3205

CPC classification number: H01L21/76892 ,  H01L21/3081 ,  H01L21/32055 ,  H01L23/49877 ,  H01L2924/0002 ,  H05K3/064 ,  H05K2201/0108 ,  H05K2201/0323 ,  H05K2201/10128 ,  H01L2924/00

Abstract: The invention provides a method for patterning a graphene layer and a method for manufacturing a display substrate. The method for patterning a graphene layer comprises: forming an isolation layer on a graphene layer; forming a photoresist layer on the isolation layer; patterning the photoresist layer; etching the isolation layer according to the patterned photoresist layer to form a patterned isolation layer; etching the graphene layer according to the patterned photoresist layer to form a patterned graphene layer; and removing the patterned isolation layer. In the method of the invention, the unfavorable condition of the prior art may be avoided that a graphene film sloughs off or a photoresist remains on a graphene film when a photoresist material is peeled off, and the product yield can be improved in the case that the production cost is controlled.

Abstract translation: 本发明提供一种用于图案化石墨烯层的方法和用于制造显示基板的方法。 图案化石墨烯层的方法包括：在石墨烯层上形成隔离层; 在隔离层上形成光致抗蚀剂层; 图案化光致抗蚀剂层; 根据图案化的光致抗蚀剂层蚀刻隔离层以形成图案化隔离层; 根据图案化的光致抗蚀剂层蚀刻石墨烯层以形成图案化的石墨烯层; 并去除图案化隔离层。 在本发明的方法中，可以避免现有技术的不利条件，当光致抗蚀剂材料被剥离时，石墨烯薄膜脱落或光致抗蚀剂残留在石墨烯薄膜上，并且在以下情况下可提高产品产率： 生产成本受到控制。

公开(公告)号：US20140087532A1

公开(公告)日：2014-03-27

申请号：US14019724

申请日：2013-09-06

Applicant: Boe Technology Group Co., Ltd.

Inventor： Bing SUN

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L27/1288 ,  H01L29/78621

Abstract: The invention provides a method for fabricating a CMOS transistor and a method for fabricating an array substrate. The method for fabricating a CMOS transistor comprises a step of forming channels, which comprises: depositing an amorphous silicon layer on a substrate, and crystallizing the amorphous silicon layer into a poly-silicon layer; implanting boron atoms into the poly-silicon layer and then forming an N channel region and a P channel region by etching the poly-silicon layer implanted with the boron atoms; forming a photoresist-partially-retained region corresponding to the N channel region and a photoresist-completely-retained region corresponding to the P channel region through a single patterning process; and removing the photoresist in the photoresist-partially-retained-region and retaining a part of the photoresist in the photoresist-completely-retained region using an ashing process, implanting phosphorus atoms through ion implantation thereby forming an N channel and a P channel.

Abstract translation: 本发明提供一种CMOS晶体管的制造方法及阵列基板的制造方法。 制造CMOS晶体管的方法包括形成通道的步骤，包括：在衬底上沉积非晶硅层，并将非晶硅层结晶成多晶硅层; 将硼原子注入到多晶硅层中，然后通过蚀刻注入硼原子的多晶硅层形成N沟道区和P沟道区; 通过单一图案化工艺形成对应于N沟道区的光致抗蚀剂部分保留区域和对应于P沟道区的光致抗蚀剂完全保留区域; 并且去除光致抗蚀剂部分保留区域中的光致抗蚀剂并且使用灰化处理将光致抗蚀剂完全保留区域中的一部分光致抗蚀剂保持在光致抗蚀剂完全保留区域中，通过离子注入植入磷原子，从而形成N沟道和P沟道。