公开(公告)号：US20180331206A1

公开(公告)日：2018-11-15

申请号：US15543726

申请日：2016-07-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jian MIN ,  Xiaolong LI ,  Tao GAO ,  Liangjian LI ,  Zhengyin XU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/027 ,  H01L21/30 ,  H01L29/36 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02675 ,  H01L21/0272 ,  H01L21/0274 ,  H01L21/3003 ,  H01L27/1285 ,  H01L27/1288 ,  H01L29/36 ,  H01L29/78618 ,  H01L29/78675

Abstract: The present application discloses a method of fabricating a polycrystalline silicon thin film transistor, the method including forming an amorphous silicon layer on a base substrate having a pattern corresponding to a polycrystalline silicon active layer of the thin film transistor; the amorphous silicon layer having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer and a second region corresponding to a channel region in the polycrystalline silicon active layer; forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; and crystallizing the amorphous silicon layer, the first dopant layer, and the second dopant layer to form the polycrystalline silicon active layer, the polycrystalline silicon active layer being doped with a dopant of the first dopant layer in the second region and doped with a dopant of the second dopant layer in the first region during the step of crystallizing the amorphous silicon layer.

公开(公告)号：US20170256631A1

公开(公告)日：2017-09-07

申请号：US15236696

申请日：2016-08-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jian MIN ,  Xiaolong LI ,  Zhengyin XU ,  Ping SONG ,  Youwei WANG

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L29/66765 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/28008 ,  H01L21/31053 ,  H01L27/1218 ,  H01L27/1229 ,  H01L27/1262 ,  H01L27/1296 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/78636 ,  H01L29/78678

Abstract: The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a gate electrode on a base substrate; forming a gate insulation layer with an even surface; forming a pattern of a polysilicon semiconductor layer; and forming patterns of a source electrode and a drain electrode. The step of forming the pattern of the polysilicon semiconductor layer includes: crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer.

公开(公告)号：US20170133475A1

公开(公告)日：2017-05-11

申请号：US15322461

申请日：2015-10-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jian MIN

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/458 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L29/45 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78675

Abstract: A low temperature poly-silicon thin film transistor and a manufacturing method thereof are disclosed. The method includes forming an active layer on a base substrate, forming an ohmic contact layer on the active layer through an atomic layer deposition process, and forming a source electrode and a drain electrode on the ohmic contact layer. The ohmic contact layer includes a plurality of conductive ionic layers and a plurality of monocrystalline silicon layers/poly-silicon layers. The source electrode and the drain electrode are in contact with the active layer through the ohmic contact layer.

公开(公告)号：US20180090712A1

公开(公告)日：2018-03-29

申请号：US15714081

申请日：2017-09-25

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ping Song ,  Feifei WANG ,  Youwei WANG ,  Peng CAI ,  Jian MIN

IPC: H01L51/52 ,  H01L51/00 ,  H01L51/56 ,  H01L27/32

CPC classification number: H01L51/5253 ,  H01L27/3244 ,  H01L51/0003 ,  H01L51/0097 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/5338 ,  Y02E10/549

Abstract: The disclosure provides a display panel and a method for manufacturing the same. The display panel includes: an underlying substrate; thin film transistors, a light emission layer, a first inorganic moisture-blocking layer successively arranged on the underlying substrate; an organic buffer layer arranged on the first inorganic moisture-blocking layer, the organic buffer layer comprises: droplet micro-structures for decentralizing a stress on the organic buffer layer; a second inorganic moisture-blocking layer arranged on the organic buffer layer; and a blocking layer, and a glass cover plate successively arranged on the second inorganic moisture-blocking layer.

公开(公告)号：US20170200745A1

公开(公告)日：2017-07-13

申请号：US15393030

申请日：2016-12-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jian MIN ,  Xiaolong LI ,  Zhengyin XU ,  Tao GAO ,  Dong LI ,  Shuai ZHANG

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1222 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/78696

Abstract: A thin film transistor, a method for fabricating the same, an array substrate, and a display device are provided. The method comprises forming an active layer on a substrate, wherein source-and-drain-to-be-formed regions of the active layer are thicker than a semiconductor region between the source-and-drain-to-be-formed regions, and by a patterning process, forming a gate on the active layer, and forming a pattern of source and drain in the source-and-drain-to-be-formed regions of the active layer.