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    ESD structure that employs a schottky-barrier to reduce the likelihood of latch-up
    1.
    发明授权
    ESD structure that employs a schottky-barrier to reduce the likelihood of latch-up 失效
    使用肖特基势垒的ESD结构减少闭锁的可能性

    公开(公告)号：US5763918A

    公开(公告)日：1998-06-09

    申请号：US740134

    申请日：1996-10-22

    申请人： Badih El-Kareh ,  James Gardner Ryan ,  Hiroyoshi Tanimoto

    发明人： Badih El-Kareh ,  James Gardner Ryan ,  Hiroyoshi Tanimoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/092 ,  H01L29/47 ,  H01L29/872 ,  H01L23/62

    CPC分类号： H01L27/0255 ,  H01L2924/0002

    摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to decrease the latch-up susceptibility of an ESD structure by suppressing the injection of minority carriers that cause transistor action to occur. This is accomplished, for example, by using a metal contact to the n-substrate or n-well in place of or in parallel with the prior art p-diffusion. Using such a metal contact forms a Schottky Barrier Diode (SBD) with the ESD structure. Since the SBD is a majority-carrier device, negligible minority carriers are injected when the SBD is in forward bias, thereby reducing the likelihood of latch-up.

    摘要翻译： 本发明的优选实施例克服了现有技术的局限，并且提供了一种通过抑制引起晶体管作用发生的少数载流子的注入来减小ESD结构的闭锁敏感性的装置和方法。 这是通过例如通过使用与n衬底或n阱的金属接触来代替或与现有技术的p-扩散并行来实现的。 使用这种金属接触形成具有ESD结构的肖特基势垒二极管（SBD）。 由于SBD是多数载波器件，当SBD处于正向偏置时，可以忽略少数载流子，从而降低闩锁的可能性。

    Semiconductor device, method of manufacturing semiconductor device, and system for evaluating electrical characteristics of semiconductor device
    2.
    发明授权
    Semiconductor device, method of manufacturing semiconductor device, and system for evaluating electrical characteristics of semiconductor device 失效
    半导体器件，制造半导体器件的方法以及用于评估半导体器件的电特性的系统

    公开(公告)号：US06784006B2

    公开(公告)日：2004-08-31

    申请号：US10001977

    申请日：2001-12-05

    申请人： Hiroyoshi Tanimoto ,  Toshiyuki Enda

    发明人： Hiroyoshi Tanimoto ,  Toshiyuki Enda

    IPC分类号： H01L2166

    CPC分类号： H01L22/20 ,  G01R31/2642

    摘要： A method of manufacturing a semiconductor device, comprises: forming a semiconductor element in a semiconductor active region, and calculating the generation rate of electron hole pairs generated due to impact ionization caused in the semiconductor element; calculating a volume integral of the generation rate at least in an area where the impact ionization is caused; evaluating time-dependent degradations of electrical characteristics of the semiconductor element on the basis of the volume integral; and manufacturing a semiconductor device on the basis of the evaluation.

    摘要翻译： 一种制造半导体器件的方法，包括：在半导体有源区中形成半导体元件，并计算由于在半导体元件中引起的冲击电离产生的电子空穴对的产生速率; 至少在造成碰撞电离的区域中计算发电率的体积积分; 基于体积积分来评估半导体元件的电特性的时间依赖性降低; 并在评估的基础上制造半导体器件。

    Electrical parameter evaluation system, electrical parameter evaluation method, and computer-readable recording medium for recording electrical parameter evaluation program
    3.
    发明授权
    Electrical parameter evaluation system, electrical parameter evaluation method, and computer-readable recording medium for recording electrical parameter evaluation program 失效
    电气参数评估系统，电气参数评估方法以及用于记录电气参数评估程序的计算机可读记录介质

    公开(公告)号：US06195790B1

    公开(公告)日：2001-02-27

    申请号：US09061866

    申请日：1998-04-17

    申请人： Hiroyoshi Tanimoto ,  Toshiyuki Enda ,  Naoyuki Shigyo ,  Kazuya Matsuzawa

    发明人： Hiroyoshi Tanimoto ,  Toshiyuki Enda ,  Naoyuki Shigyo ,  Kazuya Matsuzawa

    IPC分类号： G06F760

    CPC分类号： G06F17/5018 ,  G06F2217/16

    摘要： A &Dgr;Z calculator calculates difference between an inversion layer capacitance by a classical theory and an inversion layer capacitance by a quantum theory, calculates &Dgr;Z which is a thickness of a semiconductor substrate equivalent to the difference in inversion layer capacitance. A discretization mesh generator generates a Delaunay discretization mesh for a structure of the semiconductor device to be evaluated. An electrical parameter calculator calculates electrical parameters of the semiconductor device under constraint that a charge density of channel conductivity type of the semiconductor device is set to zero at discretization mesh points of the discretization mesh on an interface between an insulating film and the semiconductor substrate and at discretization mesh points of the discretization mesh in the semiconductor substrate which are located within a distance less than the stored &Dgr;Z from the interface between the insulating film and the semiconductor substrate.

    摘要翻译： DELTAZ计算器通过经典理论计算反演层电容与量子理论的反演层电容之间的差异，计算作为反转层电容差异的半导体衬底的厚度的DELTAZ。 离散网格生成器为要评估的半导体器件的结构生成Delaunay离散化网格。 电参数计算器在绝缘膜和半导体衬底之间的界面上的离散网格的离散网格点处以及半导体衬底的沟道导电类型的电荷密度设置为零的条件下计算半导体器件的电参数，并且在 半导体衬底中离散网格的离散网格点位于比绝缘膜和半导体衬底之间的界面上的存储的DELTAZ小的距离内。

    MONTE CARLO SIMULATION METHOD, SIMULATION APPARATUS, AND MEDIUM STORING SIMULATION PROGRAM
    4.
    发明申请
    MONTE CARLO SIMULATION METHOD, SIMULATION APPARATUS, AND MEDIUM STORING SIMULATION PROGRAM 审中-公开
    蒙特卡罗模拟方法，模拟装置和中型存储模拟程序

    公开(公告)号：US20100179792A1

    公开(公告)日：2010-07-15

    申请号：US12683135

    申请日：2010-01-06

    申请人： Takashi Kúrusu ,  Hiroyoshi Tanimoto

    发明人： Takashi Kúrusu ,  Hiroyoshi Tanimoto

    IPC分类号： G06F17/11

    CPC分类号： G06F17/5036

    摘要： A Monte Carlo simulation method for simulating movement of a carrier by alternately repeating a scattering process and a drift process, includes calculating, as a scattering time, a relaxation time by a Drude's formula in the scattering process, and determining a state of a carrier after the scattering, on the basis of a distribution function of a thermal equilibrium state.

    摘要翻译： 通过交替重复散射过程和漂移过程来模拟载体运动的蒙特卡罗模拟方法包括通过散射过程中的德鲁德公式计算弛豫时间作为散射时间，并确定载体的状态 基于热平衡状态的分布函数的散射。

    CAPACITOR OF DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE CAPACITOR
    6.
    发明申请
    CAPACITOR OF DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE CAPACITOR 失效
    动态随机存取存储器的电容器及制造电容器的方法

    公开(公告)号：US20100052028A1

    公开(公告)日：2010-03-04

    申请号：US12619229

    申请日：2009-11-16

    申请人： Yumi HAYASHI ,  Hayato Nasu ,  Kazumichi Tsumura ,  Takamasa Usui ,  Hiroyoshi Tanimoto

    发明人： Yumi HAYASHI ,  Hayato Nasu ,  Kazumichi Tsumura ,  Takamasa Usui ,  Hiroyoshi Tanimoto

    IPC分类号： H01L27/108

    CPC分类号： H01L29/945 ,  H01L27/10852 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

    摘要： A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.

    摘要翻译： 形成在半导体衬底上的晶体管具有通过栅极绝缘膜形成的栅电极和形成在半导体衬底中的第一和第二扩散层，第一和第二扩散层位于栅电极的两侧。 第一电极连接到晶体管的第一扩散层。 形成在第一电极上的电容器绝缘膜由包含衬底的氧化硅膜形成，该衬底的扩散速度比Cu快，并且比Cu更容易与氧反应。 形成在电容器绝缘膜上的第二电极由Cu层和含有该物质的另一Cu层中的一个形成。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
    半导体器件及其制造方法

    公开(公告)号：US20110284996A1

    公开(公告)日：2011-11-24

    申请号：US13109086

    申请日：2011-05-17

    申请人： Takashi Kurusu ,  Takashi Izumida ,  Hiroyoshi Tanimoto ,  Nobutoshi Aoki

    发明人： Takashi Kurusu ,  Takashi Izumida ,  Hiroyoshi Tanimoto ,  Nobutoshi Aoki

    IPC分类号： H01L23/58 ,  H01L21/4763

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.

    摘要翻译： 在一个实施例中，半导体器件包括衬底和设置在衬底上方的相同互连层中的多个互连。 该装置还包括多个绝缘体，其设置成埋在多个互连件之间。 此外，多个互连包括互连组，其中连续排列2N个或更多个互连，使得各互连的两个侧表面之间的线边缘粗糙度（LER）的相关系数为正，其中N为4或更大的整数 。

    Capacitor of dynamic random access memory and method of manufacturing the capacitor
    9.
    发明授权
    Capacitor of dynamic random access memory and method of manufacturing the capacitor 失效
    动态随机存取存储器的电容器和制造电容器的方法

    公开(公告)号：US07638829B2

    公开(公告)日：2009-12-29

    申请号：US11432660

    申请日：2006-05-12

    申请人： Yumi Hayashi ,  Hayato Nasu ,  Kazumichi Tsumura ,  Takamasa Usui ,  Hiroyoshi Tanimoto

    发明人： Yumi Hayashi ,  Hayato Nasu ,  Kazumichi Tsumura ,  Takamasa Usui ,  Hiroyoshi Tanimoto

    IPC分类号： H01L27/108

    CPC分类号： H01L29/945 ,  H01L27/10852 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

    摘要： A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.

    摘要翻译： 形成在半导体衬底上的晶体管具有通过栅极绝缘膜形成的栅电极和形成在半导体衬底中的第一和第二扩散层，第一和第二扩散层位于栅电极的两侧。 第一电极连接到晶体管的第一扩散层。 形成在第一电极上的电容器绝缘膜由包含衬底的氧化硅膜形成，该衬底的扩散速度比Cu快，并且比Cu更容易与氧反应。 形成在电容器绝缘膜上的第二电极由Cu层和含有该物质的另一Cu层中的一个形成。