公开(公告)号：US20230300087A1

公开(公告)日：2023-09-21

申请号：US18201060

申请日：2023-05-23

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart ,  Jay Evan Scott Peterson ,  Michael Gregory Ferrara ,  Michael E. Attig

IPC分类号： H04L49/00 ,  H04L45/745 ,  H04L47/2441 ,  H04L49/109 ,  H04L69/22 ,  H04L45/7453

CPC分类号： H04L49/3063 ,  H04L45/745 ,  H04L47/2441 ,  H04L49/109 ,  H04L69/22 ,  H04L45/7453

摘要： Some embodiments provide a network forwarding IC with packet processing pipelines, at least one of which includes a parser, a set of match-action stages, and a deparser. The parser is configured to receive a packet and generate a PHV including a first number of data containers storing data for the packet. A first match-action stage is configured to receive the PHV from the parser and expand the PHV to a second, larger number of data containers storing data for the packet. Each of a set of intermediate match-action stage is configured to receive the expanded PHV from a previous stage and provide the expanded PHV to a subsequent stage. A final match-action stage is configured to receive the expanded PHV and reduce the PHV to the first number of data containers. The deparser is configured to receive the reduced PHV from the final match-action stage and reconstruct the packet.

公开(公告)号：US11425038B2

公开(公告)日：2022-08-23

申请号：US16695044

申请日：2019-11-25

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart

IPC分类号： H04L12/741 ,  H04L12/933 ,  H04L45/745 ,  H04L45/00 ,  H04L49/101 ,  H04L45/64 ,  H04L49/1546 ,  H04L69/22 ,  H04L45/74 ,  H04L45/42

摘要： Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

公开(公告)号：US11411870B2

公开(公告)日：2022-08-09

申请号：US16573847

申请日：2019-09-17

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart

IPC分类号： H04L12/741 ,  H04L12/933 ,  H04L45/745 ,  H04L45/00 ,  H04L49/101 ,  H04L45/64 ,  H04L49/1546 ,  H04L69/22 ,  H04L45/74 ,  H04L45/42

摘要： Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

公开(公告)号：US11258703B1

公开(公告)日：2022-02-22

申请号：US15927859

申请日：2018-03-21

申请人： Barefoot Networks, Inc.

发明人： Steven Licking ,  Jeongkeun Lee ,  Patrick Bosshart ,  Anurag Agrawal ,  Michael Gregory Ferrara ,  Jay Evan Scott Peterson

IPC分类号： H04L12/721 ,  H04L12/801 ,  H04L12/851 ,  H04L12/751 ,  H04L45/00 ,  H04L47/11 ,  H04L47/2483 ,  H04L41/22

摘要： Some embodiments provide a data-plane forwarding circuit that can be configured to learn about a new message flow and to maintain metadata about the new message flow without first having a control plane first configure the data plane to maintain metadata about the flow. To perform its forwarding operations, the data plane includes several data message processing stages that are configured to process the data tuples associated with the data messages received by the data plane. In some embodiments, parts of the data plane message-processing stages are also configured to operate as a flow-tracking circuit that includes (1) a flow-identifying circuit to identify message flows received by the data plane, and (2) a first set of storages to store metadata about the identified flows.

公开(公告)号：US10826840B1

公开(公告)日：2020-11-03

申请号：US15835242

申请日：2017-12-07

申请人： Barefoot Networks, Inc.

发明人： Jay Evan Scott Peterson ,  Michael Gregory Ferrara ,  Anurag Agrawal ,  Patrick Bosshart ,  Jeongkeun Lee

IPC分类号： H04L12/863 ,  H04L12/741 ,  H04L12/935

摘要： Some embodiments provide a method for a packet processing pipeline of a network forwarding integrated circuit. The method stores two copies of a stateful table used by the packet processing pipeline. The stateful table is modified according to data processed by the packet processing pipeline. Upon receiving data to write to the stateful table, the method generates (i) a first copy of the received data along with an indicator for a first one of the copies of the stateful table and (ii) a second copy of the received data along with an indicator for a second one of the copies of the stateful table. The method sends the first copy of the received data into the packet processing pipeline before sending the second copy of the received data into the packet processing pipeline.

公开(公告)号：US10268634B1

公开(公告)日：2019-04-23

申请号：US15365887

申请日：2016-11-30

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart ,  Changhoon Kim

IPC分类号： G06F3/06 ,  G06F16/22 ,  G06F12/00

摘要： Some embodiments of the invention provide novel methods for storing data in a hash-addressed memory and retrieving stored data from the hash-addressed memory. In some embodiments, the method receives a search key and a data tuple. The method then uses a first hash function to generate a first hash value from the search key, and then uses this first hash value to identify an address in the hash-addressed memory. The method also uses a second hash function to generate a second hash value, and then stores this second hash value along with the data tuple in the memory at the address specified by the first hash value. To retrieve data from the hash-addressed memory, the method of some embodiments receives a search key. The method then uses the first hash function to generate a first hash value from the search key, and then uses this first hash value to identify an address in the hash-addressed memory. At the identified address, the hash-addressed memory stores a second hash value and a data tuple. The method retrieves a second hash value from the memory at the identified address, and compares this second hash value with a third hash value that the method generates from the search key by using the second hash function. When the second and third hash values match, the method retrieves the data tuple that the memory stores at the identified address.

公开(公告)号：US10127983B1

公开(公告)日：2018-11-13

申请号：US15682323

申请日：2017-08-21

申请人： Barefoot Networks, Inc.

发明人： Jay E. S. Peterson ,  Patrick Bosshart ,  Michael G. Ferrara

IPC分类号： H04L29/06 ,  G11C15/04 ,  G11C29/44 ,  G11C29/00 ,  G11C15/02

摘要： A hardware forwarding element is provided that includes a group of unit memories, a set of packet processing pipelines, and an error signal fabric. Each packet processing pipeline includes several of match action stages. Each match action stage includes a set of match action tables stored in a set of unit memories. Each unit memory is configured to detect an error in the unit memory and generate an error output when an error is detected in the memory unit. The error signal fabric, for each match action stage, combines error outputs of the unit memories storing match tables into a first bit in the error signal fabric. The error signal fabric, for each match action stage, combines error outputs of the unit memories storing action tables into a second bit in the error signal fabric.

公开(公告)号：US10063479B2

公开(公告)日：2018-08-28

申请号：US14507814

申请日：2014-10-06

申请人： Barefoot Networks, Inc.

发明人： Changhoon Kim ,  Patrick Bosshart

IPC分类号： H04J1/16 ,  H04L12/803 ,  H04L12/931 ,  H04L12/933 ,  H04L12/743 ,  H04L29/12

CPC分类号： H04L47/125 ,  H04L45/7453 ,  H04L49/10 ,  H04L49/354 ,  H04L61/20 ,  H04L61/2521

摘要： Some embodiments of the invention provide a load balancer for distributing packet flows that are addressed to a group of data compute nodes (DCNs) amongst the DCNs of the group. In some embodiments, the load balancer includes a connection data storage comprising several different destination network address translation (DNAT) tables. Each particular DNAT table is defined at a particular instance in time and stores the identity of a plurality DCNs that are part of the group at the particular instance in time. Each time a DCN is added to the group, the load balancer of some embodiments creates a new DNAT table in the connection data storage for processing new packet flows, while using previously created DNAT tables to process packets that are part of previously processed packet flows.

公开(公告)号：US09912610B2

公开(公告)日：2018-03-06

申请号：US14863961

申请日：2015-09-24

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart ,  Jay Evan Scott Peterson ,  Michael Gregory Ferrara ,  Changhoon Kim ,  Steven Licking ,  Chaitanya Kodeboyina

IPC分类号： H04L12/931 ,  H04L12/00 ,  H04L12/26

CPC分类号： H04L49/00 ,  H04L12/00 ,  H04L43/0864

摘要： A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

公开(公告)号：US20160246507A1

公开(公告)日：2016-08-25

申请号：US14968847

申请日：2015-12-14

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart

IPC分类号： G06F3/06

CPC分类号： G06F3/0635 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0683 ,  G06F13/28 ,  H04L45/54 ,  H04L45/64

摘要： Some embodiments provide a method for configuring unit memories to implement first and second sets of entries, the second set of which references the first set. The method configures a first pool of memories to implement the first set. Each first-set entry is located at a particular location in at least one of the first-pool memories. The method configures a second pool of memories to implement the second set of entries. Each second-set entry includes (i) a first set of bits for indicating a memory page that corresponds to one or more first-pool memories, (ii) a second set of bits for specifying a location in each of the one or more memories from which to retrieve data for the referenced first-set entry, and (iii) a third set of bits for specifying a sub-location within the retrieved data. The number of bits in the third set of bits is fixed for the second-set entries while a number of sub-locations varies for different locations specified by the second set of bits of different second-set entries.

摘要翻译： 一些实施例提供了一种用于配置单元存储器以实现第一和第二组条目的方法，其中第二组引用第一组。 该方法配置第一个存储池以实现第一组。 每个第一组条目位于至少一个第一池存储器中的特定位置。 该方法配置第二存储池以实现第二组条目。 每个第二组条目包括（i）用于指示对应于一个或多个第一池存储器的存储器页面的第一组位，（ii）用于指定一个或多个存储器中的每个存储器中的位置的第二组位 从中检索所引用的第一组条目的数据，以及（iii）用于指定检索的数据内的子位置的第三组位。 对于第二组条目，第三组位中的位数是固定的，而对于由不同第二组条目的第二组位指定的不同位置，多个子位置变化。