公开(公告)号：US12206599B2

公开(公告)日：2025-01-21

申请号：US18435517

申请日：2024-02-07

Applicant: Barefoot Networks, Inc.

Inventor： Xiaozhou Li ,  Jeongkeun Lee ,  Changhoon Kim ,  John Nathan Foster

IPC: H04L49/00 ,  G06F3/06 ,  H04L45/00 ,  H04L45/74 ,  H04L45/745

Abstract: Some embodiments of the invention provide a forwarding element (e.g., a switch, a router, etc.) that has one or more data plane, message-processing pipelines with key-value processing circuits. The forwarding element's data plane key-value circuits allow the forwarding element to perform key-value services that would otherwise have to be performed by data compute nodes connected by the network fabric that includes the forwarding element. In some embodiments, the key-value (KV) services of the forwarding element and other similar forwarding elements supplement the key-value services of a distributed set of key-value servers by caching a subset of the most commonly used key-value pairs in the forwarding elements that connect the set of key-value servers with their client applications. In some embodiments, the key-value circuits of the forwarding element perform the key-value service operations at message-processing line rates at which the forwarding element forwards messages to the data compute nodes and/or to other network forwarding elements in the network fabric.

公开(公告)号：US20240073158A1

公开(公告)日：2024-02-29

申请号：US18229094

申请日：2023-08-01

Applicant: Barefoot Networks, Inc.

Inventor： Anurag AGRAWAL ,  Julianne ZHU

IPC: H04L49/201 ,  H04L45/00 ,  H04L45/24 ,  H04L45/48 ,  H04L45/7453 ,  H04L49/55 ,  H04L49/901

CPC classification number: H04L49/201 ,  H04L45/245 ,  H04L45/38 ,  H04L45/48 ,  H04L45/7453 ,  H04L49/555 ,  H04L49/557 ,  H04L49/901

Abstract: A method of multicasting packets by a forwarding element that includes several packet replicators and several egress pipelines. Each packet replicator receives a data structure associated with a multicast packet that identifies a multicast group. Each packet replicator identifies a first physical egress port of a first egress pipeline for sending the multicast packet to a member of the multicast group. The first physical egress port is a member of LAG. Each packet replicator determines that the first physical egress port is not operational and identifies a second physical port in the LAG for sending the multicast packet to the member of the multicast group. When a packet replicator is connected to the same egress pipeline as the second physical egress, the packet replicator provides the identification of the second physical egress port to the egress pipeline to send the packet to the multicast member. Otherwise the packet replicator drops the packet.

公开(公告)号：US20230412520A1

公开(公告)日：2023-12-21

申请号：US18214665

申请日：2023-06-27

Applicant: Barefoot Networks, Inc.

Inventor： Yi Li ,  Michael Feng ,  Anurag Agrawal ,  Jeongkeun Lee ,  Changhoon Kim ,  Remy Chang

IPC: H04L47/625 ,  H04L45/7453 ,  H04L41/142 ,  H04L49/00 ,  H04L43/0882 ,  H04L43/16 ,  H04L45/00 ,  H04L45/745 ,  H04L45/24 ,  H04L47/32 ,  H04L47/628 ,  H04L49/109 ,  H04L47/62 ,  H04L49/90 ,  H04L69/22

CPC classification number: H04L47/6255 ,  H04L49/101 ,  H04L41/142 ,  H04L49/3063 ,  H04L43/0882 ,  H04L43/16 ,  H04L45/72 ,  H04L45/745 ,  H04L45/245 ,  H04L47/32 ,  H04L47/628 ,  H04L49/109 ,  H04L47/62 ,  H04L49/90 ,  H04L69/22 ,  H04L45/7453

Abstract: Some embodiments provide a method for an ingress packet processing pipeline of a network forwarding integrated circuit (IC). The ingress packet processing pipeline is for receiving packets from a port of the network forwarding IC and processing the packets to assign different packets to different queues of a traffic management unit of the network forwarding IC. The method receives state data from the traffic management unit. The method stores the state data in a stateful table. The method assigns a particular packet to a particular queue based on the state data received from the traffic management unit and stored in the stateful table.

公开(公告)号：US20230300087A1

公开(公告)日：2023-09-21

申请号：US18201060

申请日：2023-05-23

Applicant: Barefoot Networks, Inc.

Inventor： Patrick Bosshart ,  Jay Evan Scott Peterson ,  Michael Gregory Ferrara ,  Michael E. Attig

IPC: H04L49/00 ,  H04L45/745 ,  H04L47/2441 ,  H04L49/109 ,  H04L69/22 ,  H04L45/7453

CPC classification number: H04L49/3063 ,  H04L45/745 ,  H04L47/2441 ,  H04L49/109 ,  H04L69/22 ,  H04L45/7453

Abstract: Some embodiments provide a network forwarding IC with packet processing pipelines, at least one of which includes a parser, a set of match-action stages, and a deparser. The parser is configured to receive a packet and generate a PHV including a first number of data containers storing data for the packet. A first match-action stage is configured to receive the PHV from the parser and expand the PHV to a second, larger number of data containers storing data for the packet. Each of a set of intermediate match-action stage is configured to receive the expanded PHV from a previous stage and provide the expanded PHV to a subsequent stage. A final match-action stage is configured to receive the expanded PHV and reduce the PHV to the first number of data containers. The deparser is configured to receive the reduced PHV from the final match-action stage and reconstruct the packet.

公开(公告)号：US11716291B1

公开(公告)日：2023-08-01

申请号：US17346035

申请日：2021-06-11

Applicant: Barefoot Networks, Inc.

Inventor： Anurag Agrawal ,  Julianne Zhu

IPC: H04W56/00 ,  H04L49/201 ,  H04L49/55 ,  H04L45/7453 ,  H04L45/48 ,  H04L49/901 ,  H04L45/00 ,  H04L45/24

CPC classification number: H04L49/201 ,  H04L45/245 ,  H04L45/38 ,  H04L45/48 ,  H04L45/7453 ,  H04L49/555 ,  H04L49/557 ,  H04L49/901

Abstract: A method of multicasting packets by a forwarding element that includes several packet replicators and several egress pipelines. Each packet replicator receives a data structure associated with a multicast packet that identifies a multicast group. Each packet replicator identifies a first physical egress port of a first egress pipeline for sending the multicast packet to a member of the multicast group. The first physical egress port is a member of LAG. Each packet replicator determines that the first physical egress port is not operational and identifies a second physical port in the LAG for sending the multicast packet to the member of the multicast group. When a packet replicator is connected to the same egress pipeline as the second physical egress, the packet replicator provides the identification of the second physical egress port to the egress pipeline to send the packet to the multicast member. Otherwise the packet replicator drops the packet.

公开(公告)号：US11658923B2

公开(公告)日：2023-05-23

申请号：US17221538

申请日：2021-04-02

Applicant: Barefoot Networks, Inc.

Inventor： Masoud Moshref Javadi ,  Changhoon Kim ,  Patrick W. Bosshart ,  Anurag Agrawal

IPC: H04L12/935 ,  H04L49/00 ,  G06F9/455 ,  G06N3/08

CPC classification number: H04L49/3063 ,  G06F9/45558 ,  G06N3/08 ,  G06F2009/45595

Abstract: Some embodiments provide a network forwarding element with a data-plane forwarding circuit that has a parameter collecting circuit to store and distribute parameter values computed by several machines in a network. In some embodiments, the machines perform distributed computing operations, and the parameter values that compute are parameter values associated with the distributed computing operations. The parameter collecting circuit of the data-plane forwarding circuit (data plane) in some embodiments (1) stores a set of parameter values computed and sent by a first set of machines, and (2) distributes the collected parameter values to a second set of machines once it has collected the set of parameter values from all the machines in the first set. The first and second sets of machines are the same set of machines in some embodiments, while they are different sets of machines (e.g., one set has at least one machine that is not in the other set) in other embodiments. In some embodiments, the parameter collecting circuit performs computations on the parameter values that it collects and distributes the result of the computations once it has processed all the parameter values distributed by the first set of machines. The computations are aggregating operations (e.g., adding, averaging, etc.) that combine corresponding subset of parameter values distributed by the first set of machines.

公开(公告)号：US11546273B2

公开(公告)日：2023-01-03

申请号：US16945012

申请日：2020-07-31

Applicant: Barefoot Networks, Inc.

Inventor： Masoud Moshref Javadi ,  Changhoon Kim ,  Patrick W. Bosshart ,  Anurag Agrawal

IPC: H04L12/935 ,  H04L49/00 ,  G06F9/455 ,  G06N3/08

Abstract: Some embodiments provide a network forwarding element with a data-plane forwarding circuit that has a parameter collecting circuit to store and distribute parameter values computed by several machines in a network. In some embodiments, the machines perform distributed computing operations, and the parameter values that compute are parameter values associated with the distributed computing operations. The parameter collecting circuit of the data-plane forwarding circuit (data plane) in some embodiments (1) stores a set of parameter values computed and sent by a first set of machines, and (2) distributes the collected parameter values to a second set of machines once it has collected the set of parameter values from all the machines in the first set. The first and second sets of machines are the same set of machines in some embodiments, while they are different sets of machines (e.g., one set has at least one machine that is not in the other set) in other embodiments. In some embodiments, the parameter collecting circuit performs computations on the parameter values that it collects and distributes the result of the computations once it has processed all the parameter values distributed by the first set of machines. The computations are aggregating operations (e.g., adding, averaging, etc.) that combine corresponding subset of parameter values distributed by the first set of machines.

公开(公告)号：US20220353204A1

公开(公告)日：2022-11-03

申请号：US17867508

申请日：2022-07-18

Applicant: Barefoot Networks, Inc.

Inventor： Changhoon Kim ,  Xiaozhou Li ,  Anurag Agrawal ,  Julianne Zhu

IPC: H04L49/90 ,  H03M13/09 ,  H04L45/7453 ,  H04L41/08 ,  H04L41/0803 ,  H04L49/00 ,  H04L49/10 ,  H04L69/22

Abstract: Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

公开(公告)号：US11456970B1

公开(公告)日：2022-09-27

申请号：US16540741

申请日：2019-08-14

Applicant: Barefoot Networks, Inc.

Inventor： Antonin Mathieu Bas ,  Anurag Agrawal ,  Changhoon Kim

IPC: H04L49/90 ,  H04L47/50 ,  H04L49/40 ,  H04L49/104 ,  H04L43/50

Abstract: Some embodiments provide novel circuits for augmenting the functionality of a data plane circuit of a forwarding element with one or more field programmable circuits and external memory circuits. The external memories in some embodiments serve as deep buffers that receive through one or more FPGAs a set of data messages from the data plane (DP) circuit to store temporarily. In some of these embodiments, one or more of the FPGAs implement schedulers that specify when data messages should be retrieved from the external memories and provided back to the data plane circuit for forwarding through the network. For instance, in some embodiments, a particular FPGA can perform a scheduling operation for a first set of data messages stored in its associated external memory, and can direct another FPGA to perform the scheduling operation for a second set of data messages stored in the particular FPGA's associated external memory. Specifically, in these embodiments, the particular FPGA determines when the first subset of data messages stored in its associated external memory should be forwarded back to the data plane circuit to forward to data messages in the network, while directing another FPGA to determine when a second subset of data messages stored in the particular FPGA's external memory should be forwarded back to the data plane circuit.

公开(公告)号：US11425038B2

公开(公告)日：2022-08-23

申请号：US16695044

申请日：2019-11-25

Applicant: Barefoot Networks, Inc.

Inventor： Patrick Bosshart

IPC: H04L12/741 ,  H04L12/933 ,  H04L45/745 ,  H04L45/00 ,  H04L49/101 ,  H04L45/64 ,  H04L49/1546 ,  H04L69/22 ,  H04L45/74 ,  H04L45/42

Abstract: Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.