公开(公告)号：US08531222B1

公开(公告)日：2013-09-10

申请号：US13079595

申请日：2011-04-04

申请人： Barry Britton ,  Richard Booth ,  Phillip L. Johnson ,  Yang Xu ,  Tawei David Li

发明人： Barry Britton ,  Richard Booth ,  Phillip L. Johnson ,  Yang Xu ,  Tawei David Li

IPC分类号： H03L7/06

CPC分类号： H03L7/0802 ,  H03L7/095 ,  H03L7/14 ,  H03L7/18 ,  H03L2207/08

摘要： A phase locked loop (PLL) circuit is provided with selectable feedback paths. In one example, a method of operating a device includes passing a clock signal provided by a PLL circuit of the device through an internal feedback path of the PLL circuit to provide a first input signal to the PLL circuit while at least one external circuit of an external feedback path of the device is disabled during a low power operation mode of the device. The method also includes detecting a lock between the first input signal and a reference signal during the low power operation mode. The lock indicates that the clock signal is operating at a frequency used during a normal operation mode of the device. The method also includes passing the clock signal through the external feedback path to provide a second input signal to the PLL circuit. The method also includes switching from detecting a lock between the first input signal and the reference signal to detecting a lock between the second input signal and the reference signal if the external circuit is enabled for the normal operation mode.

摘要翻译： 锁相环（PLL）电路具有可选择的反馈路径。 在一个示例中，操作设备的方法包括通过PLL电路的内部反馈路径传递由该器件的PLL电路提供的时钟信号，以向PLL电路提供第一输入信号，同时至少一个外部电路 在器件的低功耗操作模式下，器件的外部反馈通路被禁止。 该方法还包括在低功率操作模式期间检测第一输入信号和参考信号之间的锁定。 锁定指示时钟信号以在设备的正常操作模式期间使用的频率操作。 该方法还包括使时钟信号通过外部反馈路径以向PLL电路提供第二输入信号。 该方法还包括如果外部电路用于正常操作模式，则从检测第一输入信号和参考信号之间的锁定切换到检测第二输入信号和参考信号之间的锁定。

公开(公告)号：US08314634B1

公开(公告)日：2012-11-20

申请号：US13079578

申请日：2011-04-04

申请人： Barry Britton ,  Richard Booth ,  Yang Xu ,  Tawei David Li

发明人： Barry Britton ,  Richard Booth ,  Yang Xu ,  Tawei David Li

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/018521 ,  H03K19/00361

摘要： Techniques are provided to reduce glitches at an output signal node when a device is switched to and from a low power operation mode. In one example, a method of operating a device includes providing power to operate a signal source of the device during a normal operation mode of the device. The method also includes passing an output signal from the signal source through a signal path to an output node during the normal operation mode. The method also includes receiving an operation mode signal to switch the device from the normal operation mode to a low power operation mode. The method also includes disabling the signal path to prevent glitches from appearing at the output node during the switch from the normal operation mode to the low power operation mode. The method also includes continuing providing power to the signal source until after the signal path is disabled.

摘要翻译： 当设备切换到低功率操作模式时，提供技术来减少输出信号节点处的毛刺。 在一个示例中，操作设备的方法包括在设备的正常操作模式期间提供用于操作设备的信号源的电力。 该方法还包括在正常操作模式期间将来自信号源的输出信号通过信号路径传送到输出节点。 该方法还包括接收操作模式信号以将设备从正常操作模式切换到低功率操作模式。 该方法还包括禁用信号路径以防止在从正常操作模式切换到低功率操作模式期间在输出节点处出现毛刺。 该方法还包括在信号路径被禁用之后继续向信号源供电。

公开(公告)号：US07605606B1

公开(公告)日：2009-10-20

申请号：US11498646

申请日：2006-08-03

申请人： Ming H. Ding ,  Sajitha Wijesuriya ,  Jun Zhao ,  Om P. Agrawal ,  Barry Britton ,  Xiaojie He

发明人： Ming H. Ding ,  Sajitha Wijesuriya ,  Jun Zhao ,  Om P. Agrawal ,  Barry Britton ,  Xiaojie He

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.

摘要翻译： 系统和方法为可编程逻辑块提供可编程逻辑块架构和路由架构。 例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个逻辑块片。 第一路由电路在可编程逻辑器件内为相应的可编程逻辑块提供全局信号路由。 第一输入路由电路从第一路由电路接收信号并将信号路由到相应的可编程逻辑块内的逻辑块片段。

公开(公告)号：US07532646B2

公开(公告)日：2009-05-12

申请号：US11064477

申请日：2005-02-23

申请人： Wai-Bor Leung ,  Barry Britton ,  Akila Subramaniam

发明人： Wai-Bor Leung ,  Barry Britton ,  Akila Subramaniam

IPC分类号： H04J3/06 ,  H04J3/02

CPC分类号： H04L25/14

摘要： A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

摘要翻译： 通道对准电路具有控制器和多个通道对准块。 每个通道对齐块同步两个或更多个通道。 控制器通过块协调通道的同步，使得（i）两个或更多个块的一个或多个组中的每一个中的信道被同步，并且（ii）每组块独立于任何其他组同步。

公开(公告)号：US08319521B1

公开(公告)日：2012-11-27

申请号：US13076300

申请日：2011-03-30

申请人： Wei Han ,  Barry Britton ,  Eric Lee ,  Zheng Chen ,  Warren Juenemann ,  Mose Wahlstrom

发明人： Wei Han ,  Barry Britton ,  Eric Lee ,  Zheng Chen ,  Warren Juenemann ,  Mose Wahlstrom

IPC分类号： H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17764 ,  H03K19/17768

摘要： A programmable logic device (PLD) is disclosed that includes a non-volatile memory; a shadow register; and a data shift register (DSR) configurable to receive control information from an external programming tool, wherein the DSR is configured to shift the control information into the shadow register if the PLD is in a first programming mode, the PLD being configurable to operate in the first programming mode using the control information stored in the shadow register without the control information being stored in the non-volatile memory.

摘要翻译： 公开了一种包括非易失性存储器的可编程逻辑器件（PLD）; 影子寄存器 以及数据移位寄存器（DSR），其被配置为从外部编程工具接收控制信息，其中所述DSR被配置为如果所述PLD处于第一编程模式，则将所述控制信息移位到所述影子寄存器中，所述PLD可配置为在 使用存储在影子寄存器中的控制信息的第一编程模式，而不将控制信息存储在非易失性存储器中。

公开(公告)号：US07599457B2

公开(公告)日：2009-10-06

申请号：US11199287

申请日：2005-08-08

申请人： Phillip Johnson ,  Zheng Chen ,  Barry Britton

发明人： Phillip Johnson ,  Zheng Chen ,  Barry Britton

IPC分类号： H04L7/02

CPC分类号： H04L7/0338 ,  H03L7/0812

摘要： In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.

摘要翻译： 在本发明的一个实施例中，时钟和数据恢复（CDR）系统具有产生多个相位偏移时钟信号的多相时钟发生器和一个或多个信道电路，每个信道电路接收（不同的）输入 数据信号和所有相位偏移时钟信号，并产生输出数据流和恢复的时钟信号。 每个通道电路具有多个数据寄存器（例如，触发器），每个数据寄存器在其时钟输入端口接收输入数据信号，并在其数据输入端口接收不同的相位偏移时钟信号， 触发器在输入数据信号的每个（上升沿）触发。 通道电路处理来自不同触发器的输出以选择合适的相位偏移时钟信号，以用于对输入数据信号进行采样以产生输出数据流，其中从所选择的相位偏移时钟产生恢复的时钟信号 信号。

公开(公告)号：US20060187966A1

公开(公告)日：2006-08-24

申请号：US11064477

申请日：2005-02-23

申请人： Wai-Bor Leung ,  Barry Britton ,  Akila Subramaniam

发明人： Wai-Bor Leung ,  Barry Britton ,  Akila Subramaniam

IPC分类号： H04J3/06

CPC分类号： H04L25/14

摘要： A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

公开(公告)号：US07554357B2

公开(公告)日：2009-06-30

申请号：US11346817

申请日：2006-02-03

申请人： Zheng (Jeff) Chen ,  Barry Britton ,  Harold Scholz

发明人： Zheng (Jeff) Chen ,  Barry Britton ,  Harold Scholz

IPC分类号： H03K19/173

CPC分类号： G06F17/5054

摘要： In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.

摘要翻译： 在一个实施例中，可编程逻辑器件包括：多路复用器，适于从多个外部串行接口存储器中选择压缩配置比特流; 串行接口处理器，适于通过多路复用器命令比特流选择; 以及适于将所选配置比特流解压缩为解压配置比特流的比特流解压缩器。

公开(公告)号：US07378872B1

公开(公告)日：2008-05-27

申请号：US11445620

申请日：2006-06-02

申请人： Om P. Agrawal ,  Barry Britton ,  Xiaojie He ,  Sajitha Wijesuriya ,  Ming H. Ding ,  Jun Zhao

发明人： Om P. Agrawal ,  Barry Britton ,  Xiaojie He ,  Sajitha Wijesuriya ,  Ming H. Ding ,  Jun Zhao

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.

摘要翻译： 本文公开了系统和方法，以根据本发明的实施例提供逻辑块片段架构和可编程逻辑块架构以及控制逻辑架构。 例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块，其中至少一个可编程逻辑块具有至少第一，第二和第三逻辑块片 不同的逻辑块片类型。

公开(公告)号：US06873187B1

公开(公告)日：2005-03-29

申请号：US10400705

申请日：2003-03-27

申请人： William Andrews ,  Barry Britton ,  Xiaotao Chen ,  John P. Fishburn ,  Harold Scholz

发明人： William Andrews ,  Barry Britton ,  Xiaotao Chen ,  John P. Fishburn ,  Harold Scholz

IPC分类号： G06F1/10 ,  H03K5/135 ,  H03K5/15 ,  H03K19/00

CPC分类号： G06F1/10 ,  H03K5/135 ,  H03K5/1506

摘要： An electronic circuit includes delay selection units each associated with a flip-flop or other circuit element. The delay selection unit for a given one of the circuit elements is coupled between a source of a clock or other signal and a corresponding input of the circuit element, and is controllable to provide one of a number of selectable delays for the signal. One or more of the delay selection units are controlled so as to select a particular one of the selectable delays for each of the units. In an illustrative embodiment, the particular delays may be determined at least in part based on the solution of an integer nonlinear program in which the plurality of delays for a given one of the delay selection units are arranged substantially in a monotonically increasing manner and each of at least a subset of the selectable delays for the given one of the delay selection units is specified by upper and lower bounds on the corresponding delay. The integer nonlinear program comprises a system of monotone difference constraints on finite integer ranges, and is solvable utilizing a modified Bellman-Ford algorithm.

摘要翻译： 电子电路包括每个与触发器或其他电路元件相关联的延迟选择单元。 用于给定一个电路元件的延迟选择单元耦合在时钟源或其它信号和电路元件的对应输入之间，并且可控制以提供信号的多个可选延迟中的一个。 控制一个或多个延迟选择单元以便为每个单元选择特定的一个可选延迟。 在说明性实施例中，可以至少部分地基于整数非线性程序的解决方案来确定特定延迟，其中给定的一个延迟选择单元的多个延迟基本上以单调增加的方式排列， 给定的一个延迟选择单元的可选延迟的至少一个子集由对应的延迟的上限和下限来指定。 整数非线性程序包括有限整数范围的单调差分约束系统，并且可以利用改进的贝尔曼 - 福特算法进行求解。