Power control block with output glitch protection
    1.
    发明授权
    Power control block with output glitch protection 有权
    电源控制块,带有输出毛刺保护

    公开(公告)号:US08314634B1

    公开(公告)日:2012-11-20

    申请号:US13079578

    申请日:2011-04-04

    IPC分类号: H03K17/16 H03K19/003

    摘要: Techniques are provided to reduce glitches at an output signal node when a device is switched to and from a low power operation mode. In one example, a method of operating a device includes providing power to operate a signal source of the device during a normal operation mode of the device. The method also includes passing an output signal from the signal source through a signal path to an output node during the normal operation mode. The method also includes receiving an operation mode signal to switch the device from the normal operation mode to a low power operation mode. The method also includes disabling the signal path to prevent glitches from appearing at the output node during the switch from the normal operation mode to the low power operation mode. The method also includes continuing providing power to the signal source until after the signal path is disabled.

    摘要翻译: 当设备切换到低功率操作模式时,提供技术来减少输出信号节点处的毛刺。 在一个示例中,操作设备的方法包括在设备的正常操作模式期间提供用于操作设备的信号源的电力。 该方法还包括在正常操作模式期间将来自信号源的输出信号通过信号路径传送到输出节点。 该方法还包括接收操作模式信号以将设备从正常操作模式切换到低功率操作模式。 该方法还包括禁用信号路径以防止在从正常操作模式切换到低功率操作模式期间在输出节点处出现毛刺。 该方法还包括在信号路径被禁用之后继续向信号源供电。

    Phase locked loop circuit with selectable feedback paths
    2.
    发明授权
    Phase locked loop circuit with selectable feedback paths 有权
    具有可选反馈路径的锁相环电路

    公开(公告)号:US08531222B1

    公开(公告)日:2013-09-10

    申请号:US13079595

    申请日:2011-04-04

    IPC分类号: H03L7/06

    摘要: A phase locked loop (PLL) circuit is provided with selectable feedback paths. In one example, a method of operating a device includes passing a clock signal provided by a PLL circuit of the device through an internal feedback path of the PLL circuit to provide a first input signal to the PLL circuit while at least one external circuit of an external feedback path of the device is disabled during a low power operation mode of the device. The method also includes detecting a lock between the first input signal and a reference signal during the low power operation mode. The lock indicates that the clock signal is operating at a frequency used during a normal operation mode of the device. The method also includes passing the clock signal through the external feedback path to provide a second input signal to the PLL circuit. The method also includes switching from detecting a lock between the first input signal and the reference signal to detecting a lock between the second input signal and the reference signal if the external circuit is enabled for the normal operation mode.

    摘要翻译: 锁相环(PLL)电路具有可选择的反馈路径。 在一个示例中,操作设备的方法包括通过PLL电路的内部反馈路径传递由该器件的PLL电路提供的时钟信号,以向PLL电路提供第一输入信号,同时至少一个外部电路 在器件的低功耗操作模式下,器件的外部反馈通路被禁止。 该方法还包括在低功率操作模式期间检测第一输入信号和参考信号之间的锁定。 锁定指示时钟信号以在设备的正常操作模式期间使用的频率操作。 该方法还包括使时钟信号通过外部反馈路径以向PLL电路提供第二输入信号。 该方法还包括如果外部电路用于正常操作模式,则从检测第一输入信号和参考信号之间的锁定切换到检测第二输入信号和参考信号之间的锁定。

    Cleaning device for downhole tools
    4.
    发明申请
    Cleaning device for downhole tools 有权
    井下工具清洗装置

    公开(公告)号:US20080010765A1

    公开(公告)日:2008-01-17

    申请号:US11820484

    申请日:2007-06-19

    申请人: Richard Booth

    发明人: Richard Booth

    IPC分类号: B08B9/027 B21D39/00

    CPC分类号: E21B37/02 Y10T29/49826

    摘要: A cleaning device connectable to a downhole tool for use within a well bore, the cleaning device comprising: a base member non-rotatably mountable to the downhole tool; and at least one sleeve member rotatably mountable to and around the base member, the sleeve member having a support member and at least one protruding member which protrudes from the support member and which, in use, contacts an inner surface of the well bore, wherein the support member comprises a bearing material.

    摘要翻译: 一种可连接到井下工具以用于井眼内的清洁装置,所述清洁装置包括:不可旋转地安装到所述井下工具的基座构件; 以及至少一个套筒构件,其可旋转地安装到所述基座构件周围并且围绕所述基座构件,所述套筒构件具有支撑构件和至少一个从所述支撑构件突出并且在使用中与所述井筒的内表面接触的突出构件,其中 支撑构件包括轴承材料。

    Downhole tool
    5.
    发明申请
    Downhole tool 有权
    井下工具

    公开(公告)号:US20070068670A1

    公开(公告)日:2007-03-29

    申请号:US11586611

    申请日:2006-10-26

    申请人: Richard Booth

    发明人: Richard Booth

    IPC分类号: E21B37/02

    CPC分类号: E21B37/02

    摘要: A downhole tool for conditioning a casing or liner. The tool includes blades having a a circumferential peripheral edge for 360 degree contact with the casing or liner and are formed from a composite material which comprises a polymeric fibre. Such polymeric fibres include Kevlar®, Twaron®, Dyneema®, Spectra® and Diolen®. Bypass channels for fluid flow past the tool are provided in either the tool body or the blades.

    摘要翻译: 用于调节套管或衬管的井下工具。 该工具包括具有与壳体或衬套360度接触的圆周周缘的刀片,并且由包含聚合物纤维的复合材料形成。 这种聚合物纤维包括Kevlar,Dyna,Spectra和Diolen。 用于流过工具的流体流动的旁路通道设置在工具主体或刀片中。

    Reduction of average-to-minimum power ratio in communications signals
    6.
    发明申请
    Reduction of average-to-minimum power ratio in communications signals 失效
    降低通信信号中的平均功率与最小功率比

    公开(公告)号:US20060227895A1

    公开(公告)日:2006-10-12

    申请号:US11442488

    申请日:2006-05-26

    IPC分类号: H04L27/00 H04L25/03

    CPC分类号: H04L25/03866

    摘要: This invention, generally speaking, modifies pulse amplitude modulated signals to reduce the ratio of average power to minimum power. The signal is modified in such a manner that the signal quality remains acceptable. The signal quality is described in terms of the Power Spectral Density (PSD) and the Error Vector Magnitude (EVM).

    摘要翻译: 本发明一般地说是修改脉冲幅度调制信号以减小平均功率与最小功率的比值。 信号被修改为使得信号质量保持可接受的方式。 根据功率谱密度(PSD)和误差矢量幅度(EVM)来描述信号质量。

    Cross-fill pattern for metal fill levels, power supply filtering, and analog circuit shielding
    7.
    发明申请
    Cross-fill pattern for metal fill levels, power supply filtering, and analog circuit shielding 有权
    金属填充水平的交叉填充图案,电源滤波和模拟电路屏蔽

    公开(公告)号:US20060124972A1

    公开(公告)日:2006-06-15

    申请号:US11339540

    申请日:2006-01-26

    IPC分类号: H01L29/768

    摘要: A cross-fill metal fill pattern technique is provided such that portions of a metal fill pattern are patterned to accomplish a secondary function. For instance, in the exemplary embodiments, ever other trace or line of interdigitated fingers is routed to a ground, while the interceding traces or lines of interdigitated fingers are routed to a power supply. In this way, a capacitor function is formed across the power supply, providing additional decoupling for the power supply. Moreover, a suitably tight cross-fill metal fill pattern (i.e., higher density of metal) provides an electrical shielding function for electromagnetic radiation passing therethrough.

    摘要翻译: 提供交叉填充金属填充图案技术,使得金属填充图案的部分被图案化以实现次要功能。 例如,在示例性实施例中,交叉指状的指状物的任何其他迹线或线路被路由到地面,而交错迹线或交叉指状物线路由到电源。 以这种方式,跨电源形成电容器功能,为电源提供额外的去耦。 此外,适当紧密的交叉填充金属填充图案(即,较高的金属密度)为通过其中的电磁辐射提供电屏蔽功能。

    Shared-array multiple-output digital-to-analog converter
    9.
    发明授权
    Shared-array multiple-output digital-to-analog converter 有权
    共享阵列多输出数模转换器

    公开(公告)号:US08164499B1

    公开(公告)日:2012-04-24

    申请号:US12813540

    申请日:2010-06-11

    IPC分类号: H03M1/00

    CPC分类号: H03M1/662 H03M1/747

    摘要: In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.

    摘要翻译: 在串行器/解串器(SerDes)接收器的示例性判决反馈均衡器(DFE)中,单个电流镜阵列由多个当前数模转换器(IDAC)功能共享。 DFE具有初始放大器级,其将初始系数COEFF0应用于输入数据信号和将附加系数(例如,COEFF1-COEFF5)应用于恢复的输出数据的不同延迟版本的(例如,五个)附加放大器级 流。 将初始和多个附加放大器级的输出相加以产生施加到时钟和数据恢复(CDR)电路的均衡数据信号。 由于均衡器功能的某些特性,可以使用单个共享电流镜阵列实现多个附加放大器级,与传统实现相比,其保留了大量的芯片面积,其中每个附加放大器级具有其自己的专用电流镜阵列。

    CHILLER WITH SETPOINT ADJUSTMENT
    10.
    发明申请
    CHILLER WITH SETPOINT ADJUSTMENT 审中-公开
    具有设定点调整的CHILLER

    公开(公告)号:US20110197601A1

    公开(公告)日:2011-08-18

    申请号:US12993696

    申请日:2008-11-19

    IPC分类号: F25B49/02 F25D17/02 F25D17/06

    摘要: A chiller system includes a compressor operable at a compressor speed between a first speed and a second speed to deliver a flow of compressed fluid to a manifold at a compressor pressure and a condenser in fluid communication with the manifold to receive the compressed fluid. A condenser fan is operable at a fan speed between a minimum fan speed and a maximum fan speed to direct a cooling flow to the condenser to cool the compressed fluid and an evaporator is positioned to receive the flow of compressed fluid and operable to cool a second fluid. A controller is operable at least partially in response to a measured temperature of the second fluid and a measured temperature of the cooling flow to determine a desired pressure and to vary the compressor speed and the fan speed such that the compressor pressure equals the desired pressure.

    摘要翻译: 冷却器系统包括可在第一速度和第二速度之间以压缩机速度运行的压缩机,以将压缩流体流以压缩机压力输送到歧管,并且冷凝器与歧管流体连通以接收压缩流体。 冷凝器风扇以最小风扇速度和最大风扇速度之间的风扇速度可操作以将冷却流引导到冷凝器以冷却压缩流体,并且蒸发器被定位成接收压缩流体流并可操作以冷却第二 流体。 控制器至少部分地响应于第二流体的测量温度和冷却流的测量温度来操作以确定期望的压力并且改变压缩机速度和风扇速度,使得压缩机压力等于期望的压力。