公开(公告)号：US20050160218A1

公开(公告)日：2005-07-21

申请号：US10761853

申请日：2004-01-20

申请人： Sun-Teck See ,  Tzu-Yih Chu ,  Ben-Wei Chen ,  Horng-yee Chou ,  Szu-Kuang Chou ,  Charles Lee

发明人： Sun-Teck See ,  Tzu-Yih Chu ,  Ben-Wei Chen ,  Horng-yee Chou ,  Szu-Kuang Chou ,  Charles Lee

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F13/405 ,  G06F3/0601 ,  G06F13/1694 ,  G06F2003/0694

摘要： A FLASH controller is disclosed. The controller comprises a USB interface unit. The USB interface unit implements a USB standard that has a bus speed equal or greater than 12 Mb/s. The controller includes an internal bus coupled to the USB interface unit; and a FLASH interface unit coupled to the internal bus. The FLASH interface unit includes FLASH controller logic that allows the throughput for access to the FLASH memory to match the speed of the USB standard. Advantages of the FLASH controller in accordance with the present invention include (1) utilizing the higher speed USB interface such as the USB 2.0 standard, which substantially increases the serial throughput between USB host and FLASH controller; (2) utilizing more advanced FLASH control logic which is implemented to raise the throughput for the FLASH memory access; (3) utilizing an intelligent algorithm to detect and access the different FLASH types, which broadens the sourcing and the supply of FLASH memory; (4) by storing the software program along with data in FLASH memory which results in the cost of the controller being reduced, and also makes the software program field changeable and upgradeable; and (5) providing high integration, which substantially reduces the overall space needed and reduces the complexity and the cost of manufacturing.

摘要翻译： 公开了一种闪存控制器。 控制器包括USB接口单元。 USB接口单元实现总线速度等于或大于12 Mb / s的USB标准。 该控制器包括耦合到USB接口单元的内部总线; 以及耦合到内部总线的FLASH接口单元。 FLASH接口单元包括FLASH控制器逻辑，允许访问闪速存储器的吞吐量与USB标准的速度相匹配。 根据本发明的闪存控制器的优点包括（1）利用诸如USB 2.0标准的更高速USB接口，其大大增加了USB主机和闪存控制器之间的串行吞吐量; （2）利用更高级的FLASH控制逻辑，其实现以提高FLASH存储器访问的吞吐量; （3）利用智能算法检测和访问不同的FLASH类型，拓宽了FLASH存储器的采购和供应; （4）通过将软件程序与FLASH存储器中的数据一起存储，从而降低控制器的成本，并使软件程序区域可以更改和升级; 和（5）提供高集成度，这大大降低了所需的总体空间并降低了制造的复杂性和成本。

公开(公告)号：US20050223158A1

公开(公告)日：2005-10-06

申请号：US10818653

申请日：2004-04-05

申请人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G06F12/00 ,  G06F13/16 ,  G11C7/10

CPC分类号： G06F13/161 ,  G06F12/0804 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C2211/5641

摘要： A multi media card (MMC) is disclosed. The MMC includes a flash controller and at least one flash memory device. The flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC. The flash controller increases the throughput by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

摘要翻译： 公开了一种多媒体卡（MMC）。 MMC包括闪存控制器和至少一个闪存设备。 闪存控制器增加至少一个闪存设备的吞吐量以匹配耦合到MMC的主机总线的速度。 闪存控制器通过执行执行预读存储器读取操作，执行写入预先存储器写入操作，增加至少一个闪速存储器件的页面寄存器的大小中的一个或多个来增加吞吐量， 存储器数据总线，执行双通道并行存储器读取操作，执行双通道并行存储器写入操作，执行写入 - 高速缓冲存储器写入操作及其任何组合。

公开(公告)号：US20050120146A1

公开(公告)日：2005-06-02

申请号：US10707277

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles Lee

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles Lee

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F3/0679 ,  Y02D10/14

摘要： A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 通用串行总线（USB）单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。 响应于USB数据包中的命令，激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US20050286284A1

公开(公告)日：2005-12-29

申请号：US10882005

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/00 ,  G11C11/34 ,  G11C16/02

CPC分类号： G11C16/02

摘要： Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories. In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.

摘要翻译： 通过使用具有闪存控制器的分配逻辑单元，单个主芯片使能被解复用到多个次级芯片中，使得能够用于多个闪存芯片或芯片。 这样做，Flash存储设备容量大大扩大。 在第一方面，一种存储器包括多个存储器; 以及耦合到所述多个存储器以用于接收单个芯片使能信号的分配逻辑单元。 分配逻辑单元将单芯片使能信号解复用到多个芯片使能信号。 多个芯片使能信号中的每一个访问多个存储器中的一个。 在第二方面，印刷电路板（PCB）包括用于提供至少一个主芯片使能信号的闪光控制器。 PCB还包括多个闪存芯片和耦合到多个闪存芯片和闪存控制器的至少一部分的至少一个分配逻辑单元。 所述分配逻辑单元接收所述至少一个芯片使能信号，并且将所述至少一个芯片使能信号解复用到多个次级芯片使能信号。 多个芯片使能信号中的每一个控制对闪存芯片之一的访问。

公开(公告)号：US20050285248A1

公开(公告)日：2005-12-29

申请号：US10881203

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/04 ,  H01L23/02 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H05K1/18

CPC分类号： G11C5/04 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory package and a chip architecture which includes stacked multiple memory chips is described. In a first aspect, a memory package comprises a substrate and a plurality of memory dies mounted on the substrate. Each die has a separate chip enable. In a second aspect, a chip architecture comprises a printed circuit board (PCB). The PCB includes a footprint. The footprint includes at least one no connect (NC) pad. The chip architecture includes a plurality of stacked memory chips mounted on the printed circuit board. Each of the plurality of stacked memory has a chip enable signal pin and also has at least one NC pin. At least one of the plurality of stacked memory chips utilizes an NC pin of another of the stacked memory chips to route the chip enable pin to at least one NC pad of the footprint. Accordingly, a system and method in accordance with the present invention provides for increased memory density within a particular space constraint by (1) providing multiple dies in a single memory package and (2) by providing stacked memory chips in a single PCB footprint. In so doing, the package/PCB will have increased memory density over a conventional package/PCB within the same space constraints, and the capacity of Flash storage devices is expanded accordingly.

摘要翻译： 描述了包括堆叠的多个存储器芯片的存储器封装和芯片架构。 在第一方面，一种存储器封装包括衬底和安装在衬底上的多个存储器管芯。 每个管芯都有独立的芯片使能。 在第二方面，芯片架构包括印刷电路板（PCB）。 PCB包括一个占位面积。 足迹包括至少一个无连接（NC）垫。 芯片架构包括安装在印刷电路板上的多个堆叠的存储器芯片。 多个堆叠存储器中的每一个具有芯片使能信号引脚，并且还具有至少一个NC引脚。 多个层叠的存储器芯片中的至少一个利用另一个堆叠的存储器芯片的NC引脚将芯片使能引脚路由到占用空间的至少一个NC焊盘。 因此，根据本发明的系统和方法通过（1）在单个存储器封装中提供多个管芯并且（2）通过在单个PCB封装中提供堆叠的存储器芯片来提供特定空间约束内的增加的存储器密度。 在这样做的同时，封装/ PCB将在相同的空间限制内在传统封装/ PCB上增加存储密度，并相应地扩展闪存存储设备的容量。

公开(公告)号：US20050286283A1

公开(公告)日：2005-12-29

申请号：US10881037

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/00 ,  G11C5/06 ,  G11C16/02 ,  H05K1/18

CPC分类号： G11C16/02 ,  G06K19/077 ,  G06K19/07732 ,  H05K1/181

摘要： A Flash storage device is disclosed. The Flash storage device comprises a plurality of memories and a printed circuit board coupled to the plurality of memories. The PCB is extended beyond a predetermined dimension to accommodate the plurality of memories. By extending the length and/or the width of the PCB, additional memories can be added to the PCB, thereby adding to the memory capacity of the device.

摘要翻译： 闪存存储设备被公开。 闪存存储设备包括多个存储器和耦合到多个存储器的印刷电路板。 PCB延伸超过预定尺寸以容纳多个存储器。 通过延长PCB的长度和/或宽度，可以向PCB添加额外的存储器，从而增加了设备的存储容量。

公开(公告)号：US20050182881A1

公开(公告)日：2005-08-18

申请号：US10708634

申请日：2004-03-16

申请人： Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles Lee

发明人： Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles Lee

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/38 ,  H01R33/00

CPC分类号： G06F13/385 ,  G06K19/07732 ,  G06K19/07733 ,  H01R13/26

摘要： An extended Secure-Digital (SD) card has a second interface that uses some of the SD-interface lines. The SD card's mechanical and electrical card-interface is used, but 2 or 4 signals in the SD interface are multiplexed for use by the second interface. The second interface can have a single differential pair of serial-data lines to perform Universal-Serial-Bus (USB) transfers, or two pairs of differential data lines for Serial-Advanced-Technology-Attachment (SATA), Peripheral Component Interconnect Express (PCIE), or IEEE 1394 transfers. A card-detection routine on a host can initially use the SD interface to detect extended capabilities and command the card to switch to using the second interface. The extended SD card can communicate with legacy SD hosts using just the SD interface, and extended SD hosts can read legacy SD cards using just the SD interface, or extended SD cards using the second interface. MultiMediaCard and Memory Stick are alternatives.

摘要翻译： 扩展的安全数字（SD）卡具有使用一些SD接口线路的第二接口。 使用SD卡的机电卡接口，SD接口中的2或4个信号被复用以供第二个接口使用。 第二个接口可以具有单个差分对的串行数据线来执行通用串行总线（USB）传输，或两对差分数据线用于串行高级技术附件（SATA），外围组件互连Express（Express） PCIE）或IEEE 1394传输。 主机上的卡检测程序最初可以使用SD接口来检测扩展功能，并命令卡切换到使用第二个接口。 扩展SD卡可以使用SD接口与传统SD主机进行通信，扩展SD主机可以使用SD接口读取旧SD卡，也可以使用第二个接口读取扩展SD卡。 多媒体卡和记忆棒是替代品。

公开(公告)号：US20050204187A1

公开(公告)日：2005-09-15

申请号：US10799039

申请日：2004-03-11

申请人： Charles Lee ,  Ben-Wei Chen ,  Szu-Kuang Chou

发明人： Charles Lee ,  Ben-Wei Chen ,  Szu-Kuang Chou

IPC分类号： G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0246 ,  G06F11/141 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C29/76

摘要： A flash memory controller is disclosed. The flash memory controller includes a processor for executing at least one operation and arbitration logic coupled to the processor. Data from the arbitration logic allows the processor to perform the at least one operation for a flash memory device. In one aspect of the present invention, the processor utilizes data from the arbitration logic to direct a search for available blocks to the particular flash memory device. In another aspect of the present invention, the processor utilizes an internal buffer within the flash memory device to store valid data during the search before the valid data is relocated. As a result, the search time for available blocks is greatly shortened and the need for an external buffer is eliminated. Consequently, the speed at which block management operations are performed is significantly increased.

摘要翻译： 公开了一种闪存控制器。 闪速存储器控制器包括用于执行耦合到处理器的至少一个操作和仲裁逻辑的处理器。 来自仲裁逻辑的数据允许处理器对闪存设备执行至少一个操作。 在本发明的一个方面，处理器利用来自仲裁逻辑的数据将可用块的搜索引导到特定的闪存设备。 在本发明的另一方面，处理器利用闪速存储器件内的内部缓冲器在有效数据被重定位之前在搜索期间存储有效数据。 结果，可用块的搜索时间大大缩短，并且消除了对外部缓冲器的需要。 因此，执行块管理操作的速度显着增加。

公开(公告)号：US20080065796A1

公开(公告)日：2008-03-13

申请号：US11926636

申请日：2007-10-29

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F13/42

CPC分类号： G06F13/28 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An extended Universal-Serial Bus (EUSB) bridge to a host computer can have Peripheral Components Interconnect Express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.

摘要翻译： 到主机的扩展通用串行总线（EUSB）桥可以在桥的一侧具有外围组件互连Express（PCIE）协议层，在桥的另一侧可以具有高级桥接转换器 模块连接上层。 可以通过将桥与I / O控制器集成来消除PCIE物理，数据链路和传输层。 PCIE请求和数据有效载荷直接发送到桥，而不是低级PCIE物理信号。 PCIE数据有效载荷通过高级直接桥接转换器模块转换为EUSB数据有效载荷。 然后，EUSB数据有效载荷被传递到EUSB事务层，EUSB数据链路层和EUSB物理层，其在EUSB总线的两个差分对上驱动和感测物理电信号。

公开(公告)号：US20060002096A1

公开(公告)日：2006-01-05

申请号：US10882539

申请日：2004-06-30

申请人： Kuang-Yu Wang ,  Charles Lee ,  Horng-Yee Chou

发明人： Kuang-Yu Wang ,  Charles Lee ,  Horng-Yee Chou

IPC分类号： H05K5/03 ,  H01R13/502

CPC分类号： H05K5/0278 ,  H01R13/447 ,  H05K1/181 ,  H05K1/182 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2203/1572

摘要： The present invention relates to a method and system for providing a flash memory assembly. The flash memory assembly includes a connector and a printed circuit board (PCB) coupled to the connector. The center of the PCB is positioned substantially at the center of the connector. An electronic component is coupled to one side of the PCB. In another aspect of the present invention, a second electronic component is coupled to a second side of the PCB. In another aspect of the present invention, the electronic components and the PCB are protected by covers joined using interference fitting or ultrasonic joining. In another aspect of the present invention, a cap protects the connector. The cap can be removably coupled to the connector.

摘要翻译： 本发明涉及一种用于提供闪存组件的方法和系统。 闪存组件包括连接器和耦合到连接器的印刷电路板（PCB）。 PCB的中心基本上位于连接器的中心。 电子部件耦合到PCB的一侧。 在本发明的另一方面，第二电子部件耦合到PCB的第二侧。 在本发明的另一方面，电子部件和PCB由使用干涉配合或超声波接合连接的盖保护。 在本发明的另一方面，帽保护连接器。 盖可以可拆卸地联接到连接器。