公开(公告)号：US20050120146A1

公开(公告)日：2005-06-02

申请号：US10707277

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles Lee

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles Lee

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F3/0679 ,  Y02D10/14

摘要： A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 通用串行总线（USB）单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。 响应于USB数据包中的命令，激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US20050120157A1

公开(公告)日：2005-06-02

申请号：US10707276

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

IPC分类号： G06F13/20 ,  G06F13/38

CPC分类号： G06F13/385

摘要： A dual-mode Universal-Serial-Bus (USB) switch can operate in a normal hub mode to buffer transactions from a host to multiple USB flash storage blocks that are USB endpoints. When operating in a single-endpoint mode, the dual-mode USB switch intercepts packets from the host and responds to the host as a single USB endpoint. The USB switch aggregates all downstream USB flash storage blocks and reports a single pool of memory to the host as a single virtual USB memory. Adjacent transactions can be overlapped by packet re-ordering. A token packet that starts a following transaction is re-ordered to be sent to the USB flash storage blocks before the data and handshake packets that end a first transaction, allowing the second transaction to begin accessing the flash memory earlier. Data can be mirrored or striped across several USB flash storage blocks and parity can be added for error recovery.

摘要翻译： 双模通用串行总线（USB）交换机可以在正常集线器模式下工作，以缓冲从主机到作为USB端点的多个USB闪存存储块的事务。 当以单端点模式运行时，双模式USB交换机将拦截主机的数据包，并作为单个USB端点作为主机响应。 USB转换器将所有下游USB闪存存储块聚合，并将单个存储器池作为单个虚拟USB存储器报告给主机。 相邻的事务可以通过重新排序重叠。 在数据和握手结束第一个事务的数据包之前，重新排序启动后续事务的令牌数据包，以便在第二个事务开始之前开始访问闪存。 数据可以跨几个USB闪存存储块进行镜像或条带化，并且可以添加奇偶校验以进行错误恢复。

公开(公告)号：US20050138288A1

公开(公告)日：2005-06-23

申请号：US10746935

申请日：2003-12-23

申请人： Horng-Yee Chou ,  Ben Wei Chen ,  Sun-Teck See

发明人： Horng-Yee Chou ,  Ben Wei Chen ,  Sun-Teck See

IPC分类号： G06F12/00 ,  G06F13/40

CPC分类号： G06F13/409

摘要： A flash memory device for connecting to an ExpressCard™ host includes at least one flash memory module, an ExpressCard™ connector for connecting to the ExpressCard™ host, a first serial interface coupled to the ExpressCard™ connector, and a controller coupled to the first serial interface and the at least one flash memory module.

摘要翻译： 用于连接到ExpressCard TM主机的闪存设备包括至少一个闪存模块，用于连接到ExpressCard TM主机的ExpressCard TM连接器，耦合到ExpressCard TM连接器的第一串行接口， 以及耦合到所述第一串行接口和所述至少一个闪存模块的控制器。

公开(公告)号：US07103684B2

公开(公告)日：2006-09-05

申请号：US10707277

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles C. Lee

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles C. Lee

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/12

CPC分类号： G06F13/28 ,  G06F3/0679 ,  Y02D10/14

摘要： A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 通用串行总线（USB）单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。 响应于USB数据包中的命令，激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US07073010B2

公开(公告)日：2006-07-04

申请号：US10707276

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

IPC分类号： G06F13/20

CPC分类号： G06F13/385

摘要： A dual-mode Universal-Serial-Bus (USB) switch can operate in a normal hub mode to buffer transactions from a host to multiple USB flash storage blocks that are USB endpoints. When operating in a single-endpoint mode, the dual-mode USB switch intercepts packets from the host and responds to the host as a single USB endpoint. The USB switch aggregates all downstream USB flash storage blocks and reports a single pool of memory to the host as a single virtual USB memory. Adjacent transactions can be overlapped by packet re-ordering. A token packet that starts a following transaction is re-ordered to be sent to the USB flash storage blocks before the data and handshake packets that end a first transaction, allowing the second transaction to begin accessing the flash memory earlier. Data can be mirrored or striped across several USB flash storage blocks and parity can be added for error recovery.

摘要翻译： 双模通用串行总线（USB）交换机可以在正常集线器模式下工作，以缓冲从主机到作为USB端点的多个USB闪存存储块的事务。 当以单端点模式运行时，双模式USB交换机将拦截主机的数据包，并作为单个USB端点作为主机响应。 USB转换器将所有下游USB闪存存储块聚合，并将单个存储器池作为单个虚拟USB存储器报告给主机。 相邻的事务可以通过重新排序重叠。 在数据和握手结束第一个事务的数据包之前，重新排序启动后续事务的令牌数据包，以便在第二个事务开始之前开始访问闪存。 数据可以跨几个USB闪存存储块进行镜像或条带化，并且可以添加奇偶校验以进行错误恢复。

公开(公告)号：US20050286283A1

公开(公告)日：2005-12-29

申请号：US10881037

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/00 ,  G11C5/06 ,  G11C16/02 ,  H05K1/18

CPC分类号： G11C16/02 ,  G06K19/077 ,  G06K19/07732 ,  H05K1/181

摘要： A Flash storage device is disclosed. The Flash storage device comprises a plurality of memories and a printed circuit board coupled to the plurality of memories. The PCB is extended beyond a predetermined dimension to accommodate the plurality of memories. By extending the length and/or the width of the PCB, additional memories can be added to the PCB, thereby adding to the memory capacity of the device.

摘要翻译： 闪存存储设备被公开。 闪存存储设备包括多个存储器和耦合到多个存储器的印刷电路板。 PCB延伸超过预定尺寸以容纳多个存储器。 通过延长PCB的长度和/或宽度，可以向PCB添加额外的存储器，从而增加了设备的存储容量。

公开(公告)号：US20050223158A1

公开(公告)日：2005-10-06

申请号：US10818653

申请日：2004-04-05

申请人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Tzu-Yih Chu ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G06F12/00 ,  G06F13/16 ,  G11C7/10

CPC分类号： G06F13/161 ,  G06F12/0804 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C2211/5641

摘要： A multi media card (MMC) is disclosed. The MMC includes a flash controller and at least one flash memory device. The flash controller increases the throughput of the at least one flash memory device to match the speed of a host bus coupled to the MMC. The flash controller increases the throughput by performing one or more of performing a read-ahead memory read operation, performing a write-ahead memory write operation, increasing the size of a page register of the at least one flash memory device, increasing the width of a memory data bus, performing a dual-channel concurrent memory read operation, performing a dual-channel concurrent memory write operation, performing a write-cache memory write operation, and any combination thereof.

摘要翻译： 公开了一种多媒体卡（MMC）。 MMC包括闪存控制器和至少一个闪存设备。 闪存控制器增加至少一个闪存设备的吞吐量以匹配耦合到MMC的主机总线的速度。 闪存控制器通过执行执行预读存储器读取操作，执行写入预先存储器写入操作，增加至少一个闪速存储器件的页面寄存器的大小中的一个或多个来增加吞吐量， 存储器数据总线，执行双通道并行存储器读取操作，执行双通道并行存储器写入操作，执行写入 - 高速缓冲存储器写入操作及其任何组合。

公开(公告)号：US20050286284A1

公开(公告)日：2005-12-29

申请号：US10882005

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/00 ,  G11C11/34 ,  G11C16/02

CPC分类号： G11C16/02

摘要： Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories. In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.

摘要翻译： 通过使用具有闪存控制器的分配逻辑单元，单个主芯片使能被解复用到多个次级芯片中，使得能够用于多个闪存芯片或芯片。 这样做，Flash存储设备容量大大扩大。 在第一方面，一种存储器包括多个存储器; 以及耦合到所述多个存储器以用于接收单个芯片使能信号的分配逻辑单元。 分配逻辑单元将单芯片使能信号解复用到多个芯片使能信号。 多个芯片使能信号中的每一个访问多个存储器中的一个。 在第二方面，印刷电路板（PCB）包括用于提供至少一个主芯片使能信号的闪光控制器。 PCB还包括多个闪存芯片和耦合到多个闪存芯片和闪存控制器的至少一部分的至少一个分配逻辑单元。 所述分配逻辑单元接收所述至少一个芯片使能信号，并且将所述至少一个芯片使能信号解复用到多个次级芯片使能信号。 多个芯片使能信号中的每一个控制对闪存芯片之一的访问。

公开(公告)号：US20050285248A1

公开(公告)日：2005-12-29

申请号：US10881203

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/04 ,  H01L23/02 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H05K1/18

CPC分类号： G11C5/04 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory package and a chip architecture which includes stacked multiple memory chips is described. In a first aspect, a memory package comprises a substrate and a plurality of memory dies mounted on the substrate. Each die has a separate chip enable. In a second aspect, a chip architecture comprises a printed circuit board (PCB). The PCB includes a footprint. The footprint includes at least one no connect (NC) pad. The chip architecture includes a plurality of stacked memory chips mounted on the printed circuit board. Each of the plurality of stacked memory has a chip enable signal pin and also has at least one NC pin. At least one of the plurality of stacked memory chips utilizes an NC pin of another of the stacked memory chips to route the chip enable pin to at least one NC pad of the footprint. Accordingly, a system and method in accordance with the present invention provides for increased memory density within a particular space constraint by (1) providing multiple dies in a single memory package and (2) by providing stacked memory chips in a single PCB footprint. In so doing, the package/PCB will have increased memory density over a conventional package/PCB within the same space constraints, and the capacity of Flash storage devices is expanded accordingly.

摘要翻译： 描述了包括堆叠的多个存储器芯片的存储器封装和芯片架构。 在第一方面，一种存储器封装包括衬底和安装在衬底上的多个存储器管芯。 每个管芯都有独立的芯片使能。 在第二方面，芯片架构包括印刷电路板（PCB）。 PCB包括一个占位面积。 足迹包括至少一个无连接（NC）垫。 芯片架构包括安装在印刷电路板上的多个堆叠的存储器芯片。 多个堆叠存储器中的每一个具有芯片使能信号引脚，并且还具有至少一个NC引脚。 多个层叠的存储器芯片中的至少一个利用另一个堆叠的存储器芯片的NC引脚将芯片使能引脚路由到占用空间的至少一个NC焊盘。 因此，根据本发明的系统和方法通过（1）在单个存储器封装中提供多个管芯并且（2）通过在单个PCB封装中提供堆叠的存储器芯片来提供特定空间约束内的增加的存储器密度。 在这样做的同时，封装/ PCB将在相同的空间限制内在传统封装/ PCB上增加存储密度，并相应地扩展闪存存储设备的容量。

公开(公告)号：US20090049222A1

公开(公告)日：2009-02-19

申请号：US12254428

申请日：2008-10-20

申请人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

发明人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

摘要翻译： 兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。 控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如， 使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。 第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。 如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。