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    Read Error Recovery for Solid-State Memory Based on Cumulative Background Charges
    1.
    发明申请
    Read Error Recovery for Solid-State Memory Based on Cumulative Background Charges 有权
    基于累积背景费用读取固态存储器的错误恢复

    公开(公告)号：US20130003459A1

    公开(公告)日：2013-01-03

    申请号：US13170501

    申请日：2011-06-28

    申请人： Bengt Anders Ulriksson ,  Ara Patapoutian

    发明人： Bengt Anders Ulriksson ,  Ara Patapoutian

    IPC分类号： G11C29/42 ,  G11C16/04

    CPC分类号： G11C16/3404 ,  G11C16/3418

    摘要： A read error is determined that affects a page of solid-state, non-volatile memory. The page is associated with a selected word line that crosses a plurality of NAND strings coupled to respective grounds and bit lines. Word lines of the memory are ordered from a lower end proximate the ground to a higher end proximate the bit lines. Cumulative background charges each associated with one of the memory cells of the page are determined. The cumulative background charges are based on charge levels of respective cells of a plural subset of the word lines that are lower in order than the selected word line. A recovery operation is performed on the page using the cumulative background charges.

    摘要翻译： 确定影响固态，非易失性存储器页面的读取错误。 该页面与选定的字线相关联，该字线跨越耦合到相应接地和位线的多个NAND串。 存储器的字线从靠近地面的下端排列到靠近位线的较高端。 确定与页面的一个存储单元相关联的累积背景费用。 累积背景电荷是基于与选择的字线相比顺序低的字线的多个子集的各个单元的电荷电平。 使用累积背景费用在页面上执行恢复操作。

    Read error recovery for solid-state memory based on cumulative background charges
    2.
    发明授权
    Read error recovery for solid-state memory based on cumulative background charges 有权
    基于累积背景费用读取固态存储器的错误恢复

    公开(公告)号：US08547743B2

    公开(公告)日：2013-10-01

    申请号：US13170501

    申请日：2011-06-28

    申请人： Bengt Anders Ulriksson ,  Ara Patapoutian

    发明人： Bengt Anders Ulriksson ,  Ara Patapoutian

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3404 ,  G11C16/3418

    摘要： A read error is determined that affects a page of solid-state, non-volatile memory. The page is associated with a selected word line that crosses a plurality of NAND strings coupled to respective grounds and bit lines. Word lines of the memory are ordered from a lower end proximate the ground to a higher end proximate the bit lines. Cumulative background charges each associated with one of the memory cells of the page are determined. The cumulative background charges are based on charge levels of respective cells of a plural subset of the word lines that are lower in order than the selected word line. A recovery operation is performed on the page using the cumulative background charges.

    摘要翻译： 确定影响固态，非易失性存储器页面的读取错误。 该页面与选定的字线相关联，该字线跨越耦合到相应接地和位线的多个NAND串。 存储器的字线从靠近地面的下端排列到靠近位线的较高端。 确定与页面的一个存储单元相关联的累积背景费用。 累积背景电荷是基于与选择的字线相比顺序低的字线的多个子集的各个单元的电荷电平。 使用累积背景费用在页面上执行恢复操作。

    Multiuse Data Channel
    3.
    发明申请
    Multiuse Data Channel 审中-公开
    多用数据通道

    公开(公告)号：US20170041099A1

    公开(公告)日：2017-02-09

    申请号：US14820137

    申请日：2015-08-06

    申请人： Ara Patapoutian ,  Hieu V. Nguyen

    发明人： Ara Patapoutian ,  Hieu V. Nguyen

    IPC分类号： H04L1/00 ,  H03M13/11 ,  G11C29/52 ,  H03M13/29 ,  G06F11/10

    CPC分类号： H04L1/0045 ,  G06F11/1072 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/2906 ,  H03M13/6516 ,  H03M13/6561

    摘要： Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.

    摘要翻译： 提出了具有可选组件的数据通道，例如编码器或解码器。 此外，可以基于数据信号特性通过数据信道来处理具有不同数据信号特性的数据。 此外，数据信道可以具有独立的编码路径和独立的解码路径。 例如，具有第一数据信号特性的第一数据传输可以经由数据信道基于数据信道的第一选定组件集合进行处理，并且具有与第一数据信号特性不同的第二数据信号特性的第二数据传输可以是 通过数据信道使用数据信道中的第二组选择的组来处理。 第一选择的组件集合可以不同于第二选择的组件集合，但是可以共享一个或多个公共组件。

    Opportunistic decoding in memory systems
    6.
    发明授权
    Opportunistic decoding in memory systems 有权
    内存系统中的机会解码

    公开(公告)号：US08627175B2

    公开(公告)日：2014-01-07

    申请号：US12891490

    申请日：2010-09-27

    申请人： Ara Patapoutian ,  Bernardo Rub ,  Bruce D. Buch

    发明人： Ara Patapoutian ,  Bernardo Rub ,  Bruce D. Buch

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1008 ,  G06F11/1048 ,  G11C16/26 ,  G11C29/844 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707 ,  H03M13/45 ,  H03M13/451 ,  H03M13/458

    摘要： Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

    摘要翻译： 用于解码从非易失性固态存储器的存储器单元读取的数据的方法包括在软数据可用于解码器的时间之前尝试使用硬解码处理对硬数据进行解码。 硬数据包括关于存储在存储器单元中的数字符号的信息，而没有数据置信度信息。 软数据包括关于存储在存储单元中的数字符号和数据置信度的信息。 响应于难以实现收敛的硬解码处理，在软数据变得可用于解码器之后，使用软解码处理解码软数据。 在硬解码处理或软解码处理实现收敛之后，解码器生成解码数据的输出。

    OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES
    7.
    发明申请
    OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES 有权
    固态存储器件的外部代码保护

    公开(公告)号：US20110296272A1

    公开(公告)日：2011-12-01

    申请号：US12790120

    申请日：2010-05-28

    申请人： Bernardo Rub ,  Ara Patapoutian ,  Arvind Sridharan ,  Bruce D. Buch

    发明人： Bernardo Rub ,  Ara Patapoutian ,  Arvind Sridharan ,  Bruce D. Buch

    IPC分类号： H03M13/29 ,  G06F11/10

    CPC分类号： G06F11/1012

    摘要： Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.

    摘要翻译： 外码字可以跨越存储器设备的多个数据块，多个芯片或多个芯片，以防止存储在块，芯片和/或芯片中的数据中的错误。 固态存储器件被布置在多个数据块中，每个块包括以多页布置的存储器单元的阵列。 数据被编码成内码字和基于符号的外码字。 内码字和基于符号的外码字被存储在多个块的存储单元中。 一个或多个内部码字被存储在每个块的每个页面中，并且每个外部码字的一个或多个符号被存储在每个块的至少一个页面中。 内部码字和外部码字从存储器件读取并用于校正数据中的错误。

    Phase coefficient generation for PLL
    8.
    发明授权
    Phase coefficient generation for PLL 有权
    PLL的相位系数生成

    公开(公告)号：US08040994B1

    公开(公告)日：2011-10-18

    申请号：US11688063

    申请日：2007-03-19

    申请人： Ara Patapoutian

    发明人： Ara Patapoutian

    IPC分类号： H03D3/24

    CPC分类号： H03L7/1075

    摘要： A method and apparatus is provided for synchronizing a clock signal by generating time varying PLL phase coefficients which approximate optimal PLL phase coefficients. An acquisition mode phase coefficient is determined by adding an error signal (A) to the sample counter (k) and finding the reciprocal of the result (1/(A+k)). The reciprocal can be calculated in hardware or determined by using a lookup table. A tracking mode phase coefficient is determined based on the error signal for use in the PLL during a track a tracking period. The tracking period begins when the tracking mode coefficient is greater than the acquisition mode coefficient.

    摘要翻译： 提供了一种通过产生近似最佳PLL相位系数的时变PLL相位系数来同步时钟信号的方法和装置。 通过将采样计数器（k）的误差信号（A）相加并求出结果的倒数（1 /（A + k））来确定采集模式相位系数。 可以用硬件计算倒数或使用查找表确定倒数。 基于在跟踪期间的轨道期间在PLL中使用的误差信号来确定跟踪模式相位系数。 当跟踪模式系数大于采集模式系数时，跟踪周期开始。

    Servo positioning adjustment
    10.
    发明申请
    Servo positioning adjustment 有权
    伺服定位调整

    公开(公告)号：US20070165325A1

    公开(公告)日：2007-07-19

    申请号：US11655799

    申请日：2007-01-18

    申请人： Ara Patapoutian ,  Zoran Coric

    发明人： Ara Patapoutian ,  Zoran Coric

    IPC分类号： G11B5/596

    CPC分类号： G11B5/59627

    摘要： An apparatus and associated method for observing an analog position signal of a control object in relation to positional indicia, recalling a previously stored runout correction value associated with the positional indicia, and calculating a corrected position signal for the control object in relation to the position signal and the runout correction value.

    摘要翻译： 一种用于观察与位置标记相关的控制对象的模拟位置信号的装置和相关联的方法，回收与该位置标记相关联的先前存储的跳动校正值，以及针对该位置信号计算控制对象的校正位置信号 和跳动校正值。