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公开(公告)号：US20130334499A1
公开(公告)日：2013-12-19
申请号：US13957965
申请日：2013-08-02
申请人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yin Jin , Marko Radosavljevic , Willy Rachmady
发明人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yin Jin , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L29/06 , H01L29/775 , H01L21/762
CPC分类号： H01L29/06 , B82Y99/00 , H01L21/76205 , H01L21/76224 , H01L29/0657 , H01L29/66795 , H01L29/775 , H01L29/7854
摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
摘要翻译： 提供了一种方法。 该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。
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公开(公告)号：US20120193609A1
公开(公告)日：2012-08-02
申请号：US13442098
申请日：2012-04-09
申请人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。
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公开(公告)号：US20140061589A1
公开(公告)日：2014-03-06
申请号：US14057204
申请日：2013-10-18
申请人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/775
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。
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公开(公告)号：US08592803B2
公开(公告)日：2013-11-26
申请号：US13442098
申请日：2012-04-09
申请人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/06 , H01L29/778
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
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公开(公告)号：US20140103397A1
公开(公告)日：2014-04-17
申请号：US14141648
申请日：2013-12-27
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译： 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。
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公开(公告)号：US20140054548A1
公开(公告)日：2014-02-27
申请号：US14069880
申请日：2013-11-01
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been-Yih Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been-Yih Jin , Robert S. Chau
IPC分类号： H01L29/775 , H01L21/76 , H01L29/66
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
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公开(公告)号：US20120309173A1
公开(公告)日：2012-12-06
申请号：US13563456
申请日：2012-07-31
申请人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
发明人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译： 本公开涉及制造微电子器件的领域。 在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。
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公开(公告)号：US08168508B2
公开(公告)日：2012-05-01
申请号：US12346554
申请日：2008-12-30
申请人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
发明人： Benjamin Chu-Kung , Uday Shah , Ravi Pillarisetty , Been-Yih Jin , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L21/76
CPC分类号： H01L29/06 , B82Y99/00 , H01L21/76205 , H01L21/76224 , H01L29/0657 , H01L29/66795 , H01L29/775 , H01L29/7854
摘要： A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
摘要翻译： 提供一种方法。 该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。
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公开(公告)号：US20110147697A1
公开(公告)日：2011-06-23
申请号：US12653847
申请日：2009-12-18
申请人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
发明人： Uday Shah , Benjamin Chu-Kung , Been-Yih Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译： 本公开涉及制造微电子器件的领域。 在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。
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公开(公告)号：US08269209B2
公开(公告)日：2012-09-18
申请号：US12653847
申请日：2009-12-18
申请人： Uday Shah , Benjamin Chu-Kung , Been Y. Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
发明人： Uday Shah , Benjamin Chu-Kung , Been Y. Jin , Ravi Pillarisetty , Marko Radosavljevic , Willy Rachmady
IPC分类号： H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0669 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/78696 , H01L2221/1094
摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
摘要翻译： 本公开涉及制造微电子器件的领域。 在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。
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