公开(公告)号：US20090130314A1

公开(公告)日：2009-05-21

申请号：US12313416

申请日：2008-11-19

申请人： Bernard D. Bauman ,  Kelly L. Williams

发明人： Bernard D. Bauman ,  Kelly L. Williams

IPC分类号： B05D3/10

CPC分类号： B05D7/04 ,  B05D3/0493 ,  B05D3/067 ,  B05D3/101 ,  B05D3/104 ,  B05D7/06

摘要： The present invention describes a system for modifying polymer composite surfaces to achieve 100% adhesion to paints, coatings, adhesives, or inks. The adhesion modification technology overcomes the deficiencies of energy-based treatment technologies common with wood-like polymer composites produced using various types of fillers and reinforcements, and specifically those containing cellulose and lignin.

摘要翻译： 本发明描述了一种用于改进聚合物复合材料表面以实现与油漆，涂料，粘合剂或油墨100％粘附的系统。 粘合改性技术克服了使用各种类型的填料和增强材料生产的木质聚合物复合材料，特别是含有纤维素和木质素的能量基处理技术的缺点。

公开(公告)号：US09093421B2

公开(公告)日：2015-07-28

申请号：US13533484

申请日：2012-06-26

申请人： Karl L. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl L. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L29/4238 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7831 ,  H01L29/7848

摘要： A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage.

摘要翻译： 一种用于利用替换金属栅极处理（RMGP）来实现在栅极内具有栅极的场效应晶体管（FET）的方法和电路，以及设置有该电路所在的设计结构。 利用RMGP的场效应晶体管包括在衬底上的介电层上的大致中心的金属栅极区域中的牺牲栅极，在衬底中形成的源极和漏极，一对电介质间隔物，第一金属栅极和第二金属栅极 替换中心金属栅极区域内的牺牲栅极，以及分离第一金属栅极和第二金属栅极的第二栅极介电层。 在中心金属栅极区域的相对侧上形成相应的电触点，用于将第一金属栅极和第二金属栅极电连接到相应的电压。

公开(公告)号：US09024387B2

公开(公告)日：2015-05-05

申请号：US13532311

申请日：2012-06-25

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L21/70 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7855

摘要： A semiconductor device has a FinFET with at least two independently controllable FETs on a single fin. The fin may have a body area with a width between two vertical sides, each side has a single FET. The fin also may have a top fin area that is wider than the body area and is electrically independent from the two FETs. The top fin area may be capable of receiving a body contact structure which may be connected to an electrical conductor as to regulate the voltage in the body area of the fin.

摘要翻译： 半导体器件具有在单个鳍上具有至少两个可独立控制的FET的FinFET。 翅片可以具有宽度在两个垂直侧之间的体区，每侧具有单个FET。 翅片还可以具有比身体区域更宽的顶鳍区域，并且与两个FET电独立。 顶鳍区域可以能够接收可以连接到电导体的体接触结构，以调节翅片的体区中的电压。

公开(公告)号：US20130043544A1

公开(公告)日：2013-02-21

申请号：US13211445

申请日：2011-08-17

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823431 ,  H01L27/0886 ,  H01L29/7855

摘要： A semiconductor chip has a FinFET structure with three independently controllable FETs on a single fin. The three FETs are connected in parallel so that current will flow between a common source and a common drain if one or more of the three independently controllable FETs is turned on. The three independently controllable FETs may be used in logic gates.

摘要翻译： 半导体芯片具有FinFET结构，在单个鳍片上具有三个可独立控制的FET。 三个FET并联连接，如果三个可独立控制的FET中的一个或多个导通，则电流将在公共源极和公共漏极之间流动。 三个可独立控制的FET可用于逻辑门。

公开(公告)号：US20120268195A1

公开(公告)日：2012-10-25

申请号：US13091259

申请日：2011-04-21

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01H37/76 ,  H01L21/76

CPC分类号： H01L23/5256 ,  H01H2085/0283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function.

摘要翻译： 一种用于在不需要单独的高电流和高电压来吹送eFuse的情况下实现增强的eFuse吹扫操作的方法和eFuse电路，并且提供了主题电路所在的设计结构。 eFuse电路包括连接到在感测模式期间可操作地控制的场效应晶体管（FET）的eFuse和用于感测和吹送eFuse的吹扫模式。 eFuse电路放置在独立的电压控制的硅​​区域上。 在感测模式期间，独立的受电压控制的硅​​区域被接地，从而提供FET增加的阈值电压。 在吹扫模式期间，独立的受控硅区域被充电到电压供应电位。 通过充电的独立电压控制的硅​​区域来降低FET的阈值电压，以提供增强的FET吹扫功能。

公开(公告)号：US20120126330A1

公开(公告)日：2012-05-24

申请号：US12950013

申请日：2010-11-19

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor chip has self aligned (where a gate electrode and associated spacers define the source/drain implant with respect to the gate electrode) Field Effect Transistors (FETs) in a back end of the line (BEOL) portion of the semiconductor chip. The FETs are used to make buffer circuits in the BEOL to improve delay and signal integrity of long signal paths on the semiconductor chip.

摘要翻译： 半导体芯片具有自对准（其中栅电极和相关联的间隔件相对于栅电极限定源/漏注入）半导体芯片的线路（BEOL）部分的后端中的场效应晶体管（FET）。 这些FET用于在BEOL中制作缓冲电路，以改善半导体芯片上的长信号路径的延迟和信号完整性。

公开(公告)号：US08114747B2

公开(公告)日：2012-02-14

申请号：US12943146

申请日：2010-11-10

申请人： Phil Christopher Felice Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Kelly L. Williams

发明人： Phil Christopher Felice Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Kelly L. Williams

IPC分类号： H01L21/336

CPC分类号： H01L27/092 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0688

摘要： A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

摘要翻译： 具有单个栅电极的3-D（三维）逆变器。 单栅电极在栅电极和第一掺杂类型的第一FET（场效应晶体管）的主体之间具有第一栅极电介质，第一FET在半导体衬底中具有第一源/漏区，或在第 半导体衬底。 单栅电极在栅电极和与第一FET相反掺杂的第二FET的本体之间具有第二栅极电介质。 第二FET的第二源极/漏极区域由在第一源极/漏极区域上生长的外延层形成。

公开(公告)号：US08492207B2

公开(公告)日：2013-07-23

申请号：US13091259

申请日：2011-04-21

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L21/762

CPC分类号： H01L23/5256 ,  H01H2085/0283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function.

摘要翻译： 一种用于在不需要单独的高电流和高电压来吹送eFuse的情况下实现增强的eFuse吹扫操作的方法和eFuse电路，并且提供了主题电路所在的设计结构。 eFuse电路包括连接到在感测模式期间可操作地控制的场效应晶体管（FET）的eFuse和用于感测和吹送eFuse的吹扫模式。 eFuse电路放置在独立的电压控制的硅​​区域上。 在感测模式期间，独立的受电压控制的硅​​区域被接地，从而提供FET增加的阈值电压。 在吹扫模式期间，独立的受控硅区域被充电到电压供应电位。 通过充电的独立电压控制的硅​​区域来降低FET的阈值电压，以提供增强的FET吹扫功能。

公开(公告)号：US08395186B2

公开(公告)日：2013-03-12

申请号：US13005059

申请日：2011-01-12

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L21/00

CPC分类号： H01L29/7827

摘要： A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.

公开(公告)号：US20120267752A1

公开(公告)日：2012-10-25

申请号：US13091275

申请日：2011-04-21

申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/2652 ,  H01L21/76267 ,  H01L29/1087

摘要： A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

摘要翻译： 半导体芯片具有独立的电压控制硅区域，其是用于控制eDRAM沟槽电容器的电容值和覆盖独立电压控制的硅​​区域的场效应晶体管的阈值电压的电路元件。 独立电压控制的硅​​区域的底部或底部是与独立电压控制的硅​​区域的衬底的掺杂相反掺杂的深度注入。 独立电压控制的硅​​区域的顶部或天花板是衬底中的埋入氧化物植入物。 独立电压控制的硅​​区域的侧面是深沟槽隔离。 独立电压控制的硅​​区域的电压通过埋入氧化物形成的接触结构施加。