公开(公告)号：US5222219A

公开(公告)日：1993-06-22

申请号：US574389

申请日：1990-08-27

申请人： Bernard Stumpf ,  Mark Kline ,  Jeffrey D. Kurtze ,  Richard G. Bahr

发明人： Bernard Stumpf ,  Mark Kline ,  Jeffrey D. Kurtze ,  Richard G. Bahr

IPC分类号： G06F13/36 ,  G06F13/42

CPC分类号： G06F13/4213 ,  G06F13/36

摘要： A method for preserving data transfer order in a pipeline computer system, wherein a first block of data is transferred from a first device to at least a second device during a first computer cycle. Simultaneously, the first block of data is stored within the first device. Druing a second computer cycle, a second block of data is transferred from the first device to the second device, and an acknowledge signal is issued, indicating the success or failure of the transfer of the first block of data. If the acknowledge signal indicates a failed data transfer, a reject signal is issued and data transfer is restarted beginning with the previously failed data transaction which has been stored within the first device, and data transfer then continues with a preserved data transfer order.

摘要翻译： 一种用于在流水线计算机系统中保持数据传输顺序的方法，其中在第一计算机循环期间，第一数据块从第一设备传送到至少第二设备。 同时，第一数据块被存储在第一设备内。 在第二计算机循环中，第二数据块从第一设备传送到第二设备，并且发出确认信号，指示第一数据块传送的成功或失败。 如果确认信号指示数据传输失败，则发出拒绝信号，并从先前已经存储在第一设备中的先前失败的数据事务开始重新开始数据传输，然后数据传输继续保留数据传输顺序。

公开(公告)号：US5175829A

公开(公告)日：1992-12-29

申请号：US262495

申请日：1988-10-25

申请人： Bernard Stumpf ,  George M. Stabler ,  Richard G. Bahr ,  Stephen J. Ciavaglia ,  Barry J. Flahive ,  Hugh Lauer

发明人： Bernard Stumpf ,  George M. Stabler ,  Richard G. Bahr ,  Stephen J. Ciavaglia ,  Barry J. Flahive ,  Hugh Lauer

IPC分类号： G06F15/16 ,  G06F9/52 ,  G06F13/374 ,  G06F15/17 ,  G06F15/177

CPC分类号： G06F13/374 ,  G06F15/17

摘要： A computer system having a plurality of processors sharing common memory and data bus structures and operable to perform atomic operations which comprise several instruction actions, wherein the processor performing the atomic operation prevents memory access interruptions by other processors by locking out other processors during the atomic operation. The system bus includes signal paths accommodating bus lock request and bus lock signals which are provided and received by each processor, which signals are initiated by specific bus lock and lock release instructions added to each processor instruction set.

公开(公告)号：US4536876A

公开(公告)日：1985-08-20

申请号：US579088

申请日：1984-02-10

申请人： Richard G. Bahr ,  Thomas C. Hogan

发明人： Richard G. Bahr ,  Thomas C. Hogan

IPC分类号： H04J3/06 ,  H04L7/033 ,  H04L7/04 ,  H04L12/42 ,  H04J3/00

CPC分类号： H04L12/422 ,  H04J3/0685 ,  H04L7/0337 ,  H04L7/046

摘要： A communications network including a plurality of terminals coupled together to provide a unidirectional communications ring. Each of the terminals is coupled in series along the ring. Each terminal is adapted to transmit (at an associated data rate) a digital signal to the next downstream terminal on the ring. Each terminal is adapted to receive a digital signal at the data rate associated with the next upstream terminal. The received digital signal is applied to a phase locked loop characterized by a hold time which exceeds its lock time. The phase locked loop extracts a local timing signal for re-clocking the received digital signal. The transmission time of N bits is less than the hold time of the phase locked loop. Each terminal monitors the re-clocked signal to identify when same valued consecutive bits are received for a period less than the phase locked loop hold time, and upon such detection to cause that terminal to generate at least one transition.

摘要翻译： 一种通信网络，包括耦合在一起以提供单向通信环的多个终端。 每个端子沿着环串联耦合。 每个终端适于将数字信号（以相关联的数据速率）发送到环上的下一个下游终端。 每个终端适于以与下一个上游终端相关联的数据速率接收数字信号。 接收的数字信号被施加到锁相环，其特征在于超过其锁定时间的保持时间。 锁相环提取本地定时信号，用于对所接收的数字信号进行重新计时。 N位的传输时间小于锁相环的保持时间。 每个终端监视重新计时的信号，以便在小于锁相环保持时间的时间段内接收相同值的连续比特，并且在这种检测时，使该终端产生至少一个转换。

公开(公告)号：US5272664A

公开(公告)日：1993-12-21

申请号：US49803

申请日：1993-04-21

申请人： David Alexander ,  Michael E. Anderson ,  Richard G. Bahr ,  Martin M. Deneroff ,  Kumar Venkatasubramaniam

发明人： David Alexander ,  Michael E. Anderson ,  Richard G. Bahr ,  Martin M. Deneroff ,  Kumar Venkatasubramaniam

IPC分类号： G11C5/00 ,  H05K1/14 ,  H05K1/18 ,  G11C5/04

CPC分类号： G11C5/066 ,  G11C7/1042 ,  H05K1/141 ,  H05K1/181

摘要： A dynamic random access memory (DRAM) single in-line memory module (SIMM) having optimized physical dimensions achieves high speed and high storage capacity. The DRAM SIMM has a printed circuit board with a multi-contact connector, a plurality of DRAM sets, each set having a plurality of DRAM chips mounted on the printed circuit board, and a plurality of buffers which are also mounted on the printed circuit board. The number of buffers is equal to the number of DRAM sets. Various standard DRAM chips can be used on the SIMM to achieve different performance and storage capacity, while maintaining plug compatibility of the multi-contact connector with a memory board. The buffers buffer the control and address signals for the DRAM chips, which is necessary to keep control and address signal integrity due to the number of DRAMS. The buffers permit each DRAM to receive the necessary control and address signals in a more synchronized fashion, so that relative delays are well controlled. The multi-contact connector has a first group of pins for receiving control and address signals, a second group of pins for data input/output signals, a third group of pins for indicating the type code of the SIMM, and a fourth group of pins for power and ground connections.

摘要翻译： 具有优化物理尺寸的动态随机存取存储器（DRAM）单列直插存储器模块（SIMM）实现了高速度和高存储容量。 DRAM SIMM具有具有多接触连接器的印刷电路板，多个DRAM组，每组具有安装在印刷电路板上的多个DRAM芯片，以及还安装在印刷电路板上的多个缓冲器 。 缓冲器的数量等于DRAM组的数量。 可以在SIMM上使用各种标准DRAM芯片来实现不同的性能和存储容量，同时保持多接点连接器与存储器板的插头兼容性。 缓冲器缓冲用于DRAM芯片的控制和地址信号，这是由于DRAMS的数量而保持控制和寻址信号完整性所必需的。 缓冲器允许每个DRAM以更同步的方式接收必要的控制和寻址信号，使得相对延迟受到良好的控制。 多接触连接器具有用于接收控制和地址信号的第一组引脚，用于数据输入/输出信号的第二组引脚，用于指示SIMM的类型代码的第三组引脚和第四组引脚 用于电源和接地连接。

公开(公告)号：US4601586A

公开(公告)日：1986-07-22

申请号：US579090

申请日：1984-02-10

申请人： Richard G. Bahr ,  Daryl F. Kinney ,  Alan G. Nemeth ,  Helen S. Raizen

发明人： Richard G. Bahr ,  Daryl F. Kinney ,  Alan G. Nemeth ,  Helen S. Raizen

IPC分类号： G06F13/38 ,  G06F15/16 ,  G06F15/17 ,  H04J3/26

CPC分类号： G06F15/161 ,  G06F13/385 ,  G06F15/17

摘要： A system for transferring solicited message packets between data processors coupled on a serial communications path. A solicitor processor allocates a portion of its memory for storage of solicited message packets which might be solicited and received from at least one other data processor. The solicitor data processor defines a sequence of operations to be performed on any such received solicited message packets at that processor. The solicitor processor also transfers a solicited message parameter signal to the solicitee data processor where that signal is representative of a predetermined header portion for solicited data packets which might be generated by the solicitee data processor and transferred to the solicitor data processor. The header portion of a solicited message packet relates one or more of the sequences of operations which are to be associated with that packet. At least one of the other data processors receives any solicited message parameter signal addressed to that solicitee data processor. The solicitee processor is responsive to a received message parameter signal to generate a solicited message packet (with a header portion, as defined by the solicited message parameter signal) for transfer to the solicitor processor. The solicitor processor receives any such transmitted solicited message packet and stores that packet in the allocated portion of memory.

摘要翻译： 一种用于在耦合在串行通信路径上的数据处理器之间传送请求的消息分组的系统。 律师处理器分配其存储器的一部分用于存储可能从至少一个其他数据处理器请求和接收的所请求的消息分组。 律师数据处理器定义将在该处理器处对任何这样接收到的请求消息分组执行的操作序列。 律师处理器还将请求的消息参数信号传送到请求者数据处理器，其中该信号代表可能由请求者数据处理器生成并传送给律师数据处理器的请求数据分组的预定报头部分。 所请求的消息分组的报头部分涉及要与该分组相关联的操作序列中的一个或多个。 至少其中一个数据处理器接收寻址到该请求数据处理器的任何请求消息参数信号。 索引处理器响应于接收到的消息参数信号以产生被请求的消息分组（具有由所请求的消息参数信号定义的报头部分）以便传送到律师处理器。 律师处理器接收任何此类发送的请求消息分组，并将该分组存储在所分配的存储器部分中。

公开(公告)号：US4494233A

公开(公告)日：1985-01-15

申请号：US466109

申请日：1983-02-14

申请人： Richard G. Bahr ,  Paul B. Cohen

发明人： Richard G. Bahr ,  Paul B. Cohen

IPC分类号： H04L12/407 ,  H04L12/433 ,  H04Q9/00

CPC分类号： H04L12/417 ,  H04L12/40032 ,  H04L12/40169 ,  H04L12/42 ,  H04L12/433

摘要： A token-passing, ring-based data communications network provides a distributive method and apparatus for detecting and regenerating a lost token. The method includes, after detection of the loss of the token, transmitting at a detecting node a data packet not including a token, the data packet uniquely identifying the transmitting node as the data source. Simultaneously, the transmitting node, after transmitting the tokenless data packet, strips all incoming data from the network. If the transmitted packet is successfully received by the transmitting node, a new token is generated by the node. If the packet is not received, the node defers to an arbitration method which includes delaying a next data packet transmission for a probabilistically determined period of time. The mean time upon which the probabilistic approach is based increases with each unsuccessful data packet transmission attempt.

摘要翻译： 令牌传递，基于环的数据通信网络提供了用于检测和再生丢失令牌的分布式方法和装置。 该方法包括在检测到令牌的丢失之后，在检测节点处发送不包括令牌的数据分组，该数据分组唯一地标识发送节点作为数据源。 同时，发送节点在发送无标记数据包之后，剥离来自网络的所有传入数据。 如果发送节点成功接收到发送的分组，则由节点生成新的令牌。 如果未接收到分组，则该节点延迟仲裁方法，该方法包括延迟下一个数据分组传输的概率确定的时间段。 随着每个不成功的数据包传输尝试，概率方法的平均时间就会增加。

公开(公告)号：US4771281A

公开(公告)日：1988-09-13

申请号：US14134

申请日：1987-01-29

申请人： Thomas F. Fox ,  Richard G. Bahr

发明人： Thomas F. Fox ,  Richard G. Bahr

IPC分类号： G06F7/76 ,  H04Q1/00

CPC分类号： G06F7/762

摘要： A bit selection and routing apparatus and method selects m data signals from among its n available data inputs and groups those m signals on its output lines. The apparatus employs a two-dimensional array of signal selection elements which are multiplexing elements. The circuitry is implemented in NMOS technology using pass transistors. The apparatus can be placed in a data flow path and can pass data either unaltered, in a selection mode, in a shift mode, and in a partial data pass mode wherein an upper portion of the input word is set to a predetermined value. The selection elements are connected to route the selected input signals to selected output lines in a predetermined order.

摘要翻译： 位选择和路由设备和方法从其n个可用数据输入中选择m个数据信号，并在其输出线上对那些m个信号进行分组。 该装置采用作为复用元件的信号选择元件的二维阵列。 该电路在使用传输晶体管的NMOS技术中实现。 该装置可以被放置在数据流路径中，并且可以以选择模式，移位模式以及部分数据通过模式传递数据，其中输入字的上部被设置为预定值。 选择元件被连接以将所选择的输入信号以预定顺序路由到所选择的输出线。

公开(公告)号：US4596982A

公开(公告)日：1986-06-24

申请号：US466080

申请日：1983-02-14

申请人： Richard G. Bahr ,  Russell L. Moore

发明人： Richard G. Bahr ,  Russell L. Moore

IPC分类号： H04L12/437 ,  H04Q3/00

CPC分类号： H04L12/437

摘要： A ring communications network which is automatically reconfigured based on the detection of system defects.

摘要翻译： 基于系统缺陷检测自动重新配置的环通信网络。

公开(公告)号：US4528661A

公开(公告)日：1985-07-09

申请号：US466110

申请日：1983-02-14

申请人： Richard G. Bahr ,  Thomas C. Hogan

发明人： Richard G. Bahr ,  Thomas C. Hogan

IPC分类号： H04L29/08 ,  H04L12/42 ,  H04J3/00

CPC分类号： H04L12/422

摘要： A communications network including a plurality of terminals coupled together to provide a unidirectional communications ring. Each of the terminals is adapted to transmit (at an associated fixed data rate) a digital signal to the next downstream terminal on the ring. Each terminal is adapted to receive a digital signal at the data rate associated with the next upstream terminal. In each local terminal, there is a detector for detecting the received synchronization packets and associated data packets are generated for transmission to the next downstream terminal on the ring at a predetermined fixed data rate associated with the local terminal. The data of each transmitted data packet matches bit for bit the data of the corresponding received data packet. The number of bits in the transmit synchronization packet differs from the number of bits in the associated received synchronization packet in a manner so that the data rate for the composite packet formed by the transmitted data packet and associated synchronization data packet corresponds to the transmit data rate for the terminal. The difference varies between predetermined minimum and maximum limits, and may be zero for two terminals having substantially the same transient bit rate.

摘要翻译： 一种通信网络，包括耦合在一起以提供单向通信环的多个终端。 每个终端适于将数字信号（以相关联的固定数据速率）发送到环上的下一个下游终端。 每个终端适于以与下一个上游终端相关联的数据速率接收数字信号。 在每个本地终端中，存在用于检测接收到的同步分组的检测器，并且生成相关联的数据分组，以与本地终端相关联的预定固定数据速率传输到环上的下一个下游终端。 每个发送的数据分组的数据将相应的接收数据分组的数据的位与比特相匹配。 发送同步分组中的比特数不同于相关联的接收的同步分组中的比特数，使得由所发送的数据分组和相关联的同步数据分组形成的合成分组的数据速率对应于发送数据速率 为终端。 该差异在预定的最小和最大限制之间变化，并且对于具有基本相同的瞬时比特率的两个终端可以为零。

公开(公告)号：US5226146A

公开(公告)日：1993-07-06

申请号：US830961

申请日：1992-02-05

申请人： Andrew Milia ,  Richard G. Bahr

发明人： Andrew Milia ,  Richard G. Bahr

IPC分类号： G06F12/08

CPC分类号： G06F12/0831

摘要： A method and apparatus for selectively invalidating tag data related to data stored in high speed processor cache memory systems. The tag data to be invalidated, due to processor operations and cache memory misses, is stored in two tag stores and indicia related to the tag data to be invalidated is stored in a purge queue. Further improvement in system performance is provided by selective tag data and indicia elimination.

摘要翻译： 一种用于选择性地使与存储在高速处理器高速缓冲存储器系统中的数据相关的标签数据无效的方法和装置。 由于处理器操作和高速缓存存储器未命中而被无效的标签数据被存储在两个标签存储器中，与要被无效标签数据相关的标记被存储在清除队列中。 通过选择性标签数据和消除标记来提供系统性能的进一步改善。