Abstract:
Systems, methods, and other embodiments associated with tracking packet identifiers are described. According to one embodiment, a method includes receiving packets of data, wherein each packet includes an encoded packet identifier, the encoded packet identifier being decoded into a decoded packet identifier, and after each packet is received, incrementing a first counter and a second counter for estimating a sequential value of the decoded packet identifier.
Abstract:
A container-less JSP system is provided. An example container-less JSP system comprises a detector, a trigger module, and an invoker. The detector may be configured to detect a request initiated by a client application to invoke a JSP template. The request is a protocol-neutral Java™ interface. The trigger module may be configured to trigger the protocol-neutral Java™ interface to invoke the JSP template. The invoker may be configured to invoke the JSP template.
Abstract:
A method of managing delivery of content to end users of an application executing on an application server is disclosed. A definition of a first variant of a web page is received, the definition of the first variant specifying that an instance of a first widget is to be included in the first variant at a first region conforming to a page layout of the web page. A definition of a second variant of the web page is received, the definition of the second variant specifying that an instance of a second widget is to be included in the second variant at a second region conforming to the page layout of the web page. A comparison of the first variant and the second variant is presented with respect to a performance metric, the performance metric pertaining to an effectiveness of the web page at bringing in revenues to a network-based publication system.
Abstract:
A system-on-a-chip includes a first memory and a processor. The first memory is configured to store a boot code. The processor is configured to (i) access the first memory, and (ii) execute the boot code when booting up. The processor is configured to, while booting up, determine whether a first one-time-programmable memory has been previously programmed based on the boot code. The processor is configured to, in response to the first one-time-programmable memory not having been previously programmed based on the boot code, (i) load firmware from a second memory into a third memory, and (ii) execute the firmware loaded into the third memory. The processor is configured to, in response to the first one-time-programmable memory having been previously programmed, verify a digital signature of the firmware.
Abstract:
A method of managing delivery of content to end users of an application executing on an application server is disclosed. A definition of a first variant of a web page is received, the definition of the first variant specifying that an instance of a first widget is to be included in the first variant at a first region conforming to a page layout of the web page. A definition of a second variant of the web page is received, the definition of the second variant specifying that an instance of a second widget is to be included in the second variant at a second region conforming to the page layout of the web page. A comparison of the first variant and the second variant is presented with respect to a performance metric, the performance metric pertaining to an effectiveness of the web page at bringing in revenues to a network-based publication system.
Abstract:
A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.
Abstract:
An encoding system for a high density optical storage medium includes a conversion module that receives a data pattern and generates a code pattern based on the data pattern. A code connector module receives the code pattern, determines whether the code pattern includes a first predetermined code pattern, and outputs a substitution code pattern when the code pattern includes the first predetermined code pattern. The first predetermined code pattern includes first and second consecutive code words that include first and second bit sequences “01010*” and “??????,” respectively, “?” corresponds to an in consequential bit, and “*” corresponds to an undetermined bit.
Abstract:
A controlled release fabrication process includes shaping a precursor material into a desired configuration with a mold, supplying a curing agent from the mold to the precursor material, curing the precursor material to form a mechanically stable structure, and releasing the mechanically stable structure from the mold. Mechanically stable structures including microfabrication articles produced using the process are also described.
Abstract:
A method to optimize calls to a service by components of an application running on an application server is provided. The method includes receiving a first call and a second call, the first call made to a service by a first one of a plurality of components included in the application, and the second call made to the service by a second one of the plurality of components; selecting one of a plurality of optimizations, the plurality of optimizations including orchestrating the first call and the second call into a third call to the service; and, in response to the selecting of the orchestrating of the first call and the second call into the third call as the one of the plurality of optimizations, orchestrating the first call and the second call into the third call.
Abstract:
A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.