公开(公告)号：US06768679B1

公开(公告)日：2004-07-27

申请号：US10361378

申请日：2003-02-10

申请人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Pauling Chen

发明人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Pauling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/0491 ,  G11C16/24 ,  G11C16/26

摘要： A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.

摘要翻译： 公开了一种用于在存储器读取操作期间感测目标单元中的电流的选择电路。 根据一个实施例，选择电路包括连接到感测电路的感测电路选择器和连接到地的接地选择器。 接地选择器将目标单元的第一位线连接到地，并且感测电路选择器将目标单元的第二位线连接到感测电路。 感测电路选择器还将第一相邻单元的第三位线连接到感测电路。 第一相邻单元与目标单元共享第二位线。

公开(公告)号：US06768677B2

公开(公告)日：2004-07-27

申请号：US10302672

申请日：2002-11-22

申请人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

发明人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/24 ,  G11C7/067

摘要： A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

公开(公告)号：US06885250B1

公开(公告)日：2005-04-26

申请号：US10844116

申请日：2004-05-12

申请人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

发明人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

IPC分类号： G11C7/06 ,  G11C16/24 ,  H03F3/04 ,  G11C16/06 ,  H03F3/45

CPC分类号： G11C16/24 ,  G11C7/067

摘要： A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

摘要翻译： 公开了一种产生快速，稳定和精确的位线电压的共源共栅放大器电路。 根据一个示例性实施例，共射共基放大器电路包括具有连接到位线电压的源极和连接到输出电压的漏极的晶体管。 共源共栅放大器电路还包括具有连接到位线电压的反相输入的差分电路，连接到参考电压的非反相输入以及连接到第一晶体管的栅极的输出。 晶体管和差分电路的工作产生快速，稳定的精确位线电压。

公开(公告)号：US06771545B1

公开(公告)日：2004-08-03

申请号：US10353558

申请日：2003-01-29

申请人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

发明人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

IPC分类号： G11C1604

CPC分类号： G11C29/82 ,  G11C16/0491 ,  G11C16/3404

摘要： An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.

摘要翻译： 非易失性存储器单元的阵列包括有效的单元格列，其中数据模式可以存储在与不存储数据的损坏或非活动列相邻的位置。 存储数据模式并在其中再现数据模式的方法包括将电荷存储在活动列内的所选择的多个存储单元内。 所选择的多个存储单元表示数据模式的一部分。 识别非活动存储器单元编程模式。 非活动存储器单元编程模式识别要在其中存储电荷的所述非活动列中的所有或选定的多个存储单元，以便在存储单元的第一非活动列中周期性地存储电荷以防止过度擦除， 在批量擦除期间以及从非活性电池泄漏到相邻的活性电池。 在第一非活动列中的所选择的多个存储器单元上存储电荷。 读取在第一活动列内的每个存储单元的数据模式。

公开(公告)号：US06788583B2

公开(公告)日：2004-09-07

申请号：US10307749

申请日：2002-12-02

申请人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

发明人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

IPC分类号： G11C1606

CPC分类号： G11C7/12 ,  G11C16/0475 ,  G11C16/24

摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

摘要翻译： 一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。 高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。 位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域 线。 将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

公开(公告)号：US06744674B1

公开(公告)日：2004-06-01

申请号：US10387617

申请日：2003-03-13

申请人： Binh Quang Le ,  Pauling Chen ,  Roger Tsao

发明人： Binh Quang Le ,  Pauling Chen ,  Roger Tsao

IPC分类号： G11C1624

CPC分类号： G11C16/26 ,  G09G3/2932 ,  G09G2310/06 ,  G09G2310/066 ,  G09G2320/041 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/24

摘要： A memory circuit senses current in a target cell during a read operation. According to one exemplary embodiment, the memory circuit comprises the target cell, a first neighboring cell, and an operational amplifier. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a drain voltage. A sensing circuit is coupled at a first node to at least one of the first bit line or the second bit line. The first neighboring cell has a third bit line connected to a second node. The operational amplifier has an output terminal connected at the second node to the third bit line. The operational amplifier has a noninverting input terminal connected to said first node, and also has an inverting input terminal connected to the second node.

摘要翻译： 存储电路在读取操作期间感测目标单元中的电流。 根据一个示例性实施例，存储器电路包括目标单元，第一相邻单元和运算放大器。 第一目标单元具有连接到地的第一位线; 目标单元还具有连接到漏极电压的第二位线。 感测电路在第一节点处耦合到第一位线或第二位线中的至少一个。 第一相邻小区具有连接到第二节点的第三位线。 运算放大器具有在第二节点处连接到第三位线的输出端子。 运算放大器具有连接到所述第一节点的同相输入端子，并且还具有连接到第二节点的反相输入端子。

公开(公告)号：US06275424B1

公开(公告)日：2001-08-14

申请号：US09774509

申请日：2001-01-31

申请人： Binh Quang Le ,  Pauling Chen

发明人： Binh Quang Le ,  Pauling Chen

IPC分类号： G11C700

CPC分类号： G11C16/16 ,  H01L27/115

摘要： The present invention reduces the voltage across the gate oxide and across a junction of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within an unselected block of an electrically erasable memory during an erase operation of a selected block of the electrically erasable memory. The drain node is coupled to each respective control gate node of a plurality of core cells disposed within a well. The present invention includes a voltage generator coupled to a gate node of the high voltage transistor and to the well having the core cells disposed therein. The present invention also includes a microcontroller that controls the voltage generator to ramp up a magnitude of a well voltage applied at the well from a start ramping time when the well voltage is at a start voltage to an end ramping time when the well voltage is at an end voltage. The mictocontroller also controls the voltage generator to couple the drain node of the high voltage MOSFET to a ground node having a ground voltage for a predetermined time period after the start ramping time. The well voltage reaches an intermediate voltage at the predetermined time period after the start ramping time. The microcontroller further controls the voltage generator to uncouple the drain node of the high voltage MOSFET from the ground node at the predetermined time period after the start ramping time. In this manner, the drain node of the high voltage MOSFET has a controlled voltage, with a magnitude that is substantially equal to a magnitude of the end voltage minus a magnitude of the intermediate voltage, at the end ramping time when the well voltage is at the end voltage.

摘要翻译： 本发明在电可擦除存储器的选定块的擦除操作期间降低栅电氧化物两端的电压，并跨越电可擦除存储器的未选择块内的高电压MOSFET（金属氧化物半导体场效应晶体管）的结。 漏极节点耦合到设置在阱内的多个核心单元的每个相应的控制栅极节点。 本发明包括耦合到高压晶体管的栅极节点的电压发生器和其中设置有核心单元的阱。 本发明还包括一个微控制器，其控制电压发生器，当井电压处于起始电压时，当井电压处于起始电压时到达结束斜坡时间时，从起始斜坡时间斜坡上升施加在井处的阱电压的幅度 结束电压。 微控制器还控制电压发生器，以在开始斜坡时间之后的预定时间段内将高压MOSFET的漏极节点耦合到具有接地电压的接地节点。 在开始斜坡时间之后的预定时间段，阱电压达到中间电压。 微控制器进一步控制电压发生器在开始斜坡时间之后的预定时间段从接地节点将高压MOSFET的漏极节点断开。 以这种方式，高压MOSFET的漏极节点具有受控电压，其幅度基本上等于终端电压的幅度减去中间电压的幅度，当阱电压在 结束电压。

公开(公告)号：US06240017B1

公开(公告)日：2001-05-29

申请号：US09353267

申请日：1999-07-14

申请人： Binh Quang Le ,  Pauling Chen

发明人： Binh Quang Le ,  Pauling Chen

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  H01L27/115

摘要： The present invention reduces the voltage across the gate oxide and across a junction of a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) within an unselected block of an electrically erasable memory during an erase operation of a selected block of the electrically erasable memory. The drain node is coupled to each respective control gate node of a plurality of core cells disposed within a well. The present invention includes a voltage generator coupled to a gate node of the high voltage transistor and to the well having the core cells disposed therein. The present invention also includes a microcontroller that controls the voltage generator to ramp up a magnitude of a well voltage applied at the well from a start ramping time when the well voltage is at a start voltage to an end ramping time when the well voltage is at an end voltage. The microcontroller also controls the voltage generator to couple the drain node of the high voltage MOSFET to a ground node having a ground voltage for a predetermined time period after the start ramping time. The well voltage reaches an intermediate voltage at the predetermined time period after the start ramping time. The microcontroller further controls the voltage generator to uncouple the drain node of the high voltage MOSFET from the ground node at the predetermined time period after the start ramping time. In this manner, the drain node of the high voltage MOSFET has a controlled voltage, with a magnitude that is substantially equal to a magnitude of the end voltage minus a magnitude of the intermediate voltage, at the end ramping time when the well voltage is at the end voltage.

摘要翻译： 本发明在电可擦除存储器的选定块的擦除操作期间降低栅电氧化物两端的电压，并跨越电可擦除存储器的未选择块内的高电压MOSFET（金属氧化物半导体场效应晶体管）的结。 漏极节点耦合到设置在阱内的多个核心单元的每个相应的控制栅极节点。 本发明包括耦合到高压晶体管的栅极节点的电压发生器和其中设置有核心单元的阱。 本发明还包括一个微控制器，其控制电压发生器，当井电压处于起始电压时，当井电压处于起始电压时到达结束斜坡时间时，从起始斜坡时间斜坡上升施加在井处的阱电压的幅度 结束电压。 微控制器还控制电压发生器将高压MOSFET的漏极节点连接到具有接地电压的接地节点，该接地节点在启动斜坡时间之后的预定时间段内。 在开始斜坡时间之后的预定时间段，阱电压达到中间电压。 微控制器进一步控制电压发生器在开始斜坡时间之后的预定时间段从接地节点将高压MOSFET的漏极节点断开。 以这种方式，高压MOSFET的漏极节点具有受控电压，其幅度基本上等于终端电压的幅度减去中间电压的幅度，当阱电压在 结束电压。