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33 条记录 (耗时 0.027 秒)

    Selection circuit for accurate memory read operations
    1.
    发明授权
    Selection circuit for accurate memory read operations 有权
    选择电路，用于精确的存储器读操作

    公开(公告)号：US06768679B1

    公开(公告)日：2004-07-27

    申请号：US10361378

    申请日：2003-02-10

    申请人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Pauling Chen

    发明人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Pauling Chen

    IPC分类号： G11C1606

    CPC分类号： G11C16/0491 ,  G11C16/24 ,  G11C16/26

    摘要： A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.

    摘要翻译： 公开了一种用于在存储器读取操作期间感测目标单元中的电流的选择电路。 根据一个实施例，选择电路包括连接到感测电路的感测电路选择器和连接到地的接地选择器。 接地选择器将目标单元的第一位线连接到地，并且感测电路选择器将目标单元的第二位线连接到感测电路。 感测电路选择器还将第一相邻单元的第三位线连接到感测电路。 第一相邻单元与目标单元共享第二位线。

    Cascode amplifier circuit for producing a fast, stable and accurate bit line voltage
    2.
    发明授权
    Cascode amplifier circuit for producing a fast, stable and accurate bit line voltage 有权

    公开(公告)号：US06768677B2

    公开(公告)日：2004-07-27

    申请号：US10302672

    申请日：2002-11-22

    申请人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

    发明人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

    IPC分类号： G11C1606

    CPC分类号： G11C16/24 ,  G11C7/067

    摘要： A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

    Cascode amplifier circuit for generating and maintaining a fast, stable and accurate bit line voltage
    3.
    发明授权
    Cascode amplifier circuit for generating and maintaining a fast, stable and accurate bit line voltage 有权
    串行放大器电路，用于产生和保持快速，稳定和精确的位线电压

    公开(公告)号：US06885250B1

    公开(公告)日：2005-04-26

    申请号：US10844116

    申请日：2004-05-12

    申请人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

    发明人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

    IPC分类号： G11C7/06 ,  G11C16/24 ,  H03F3/04 ,  G11C16/06 ,  H03F3/45

    CPC分类号： G11C16/24 ,  G11C7/067

    摘要： A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

    摘要翻译： 公开了一种产生快速，稳定和精确的位线电压的共源共栅放大器电路。 根据一个示例性实施例，共射共基放大器电路包括具有连接到位线电压的源极和连接到输出电压的漏极的晶体管。 共源共栅放大器电路还包括具有连接到位线电压的反相输入的差分电路，连接到参考电压的非反相输入以及连接到第一晶体管的栅极的输出。 晶体管和差分电路的工作产生快速，稳定的精确位线电压。

    Circuit for accurate memory read operations
    4.
    发明授权
    Circuit for accurate memory read operations 有权
    电路用于精确的存储器读取操作

    公开(公告)号：US06731542B1

    公开(公告)日：2004-05-04

    申请号：US10313444

    申请日：2002-12-05

    申请人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Chen Pauling

    发明人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Chen Pauling

    IPC分类号： G11C1606

    CPC分类号： G11C16/26 ,  G11C16/0491

    摘要： A memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.

    摘要翻译： 公开了一种用于在读取操作期间感测目标单元中的电流的存储器电路装置。 根据一个示例性实施例，存储器电路装置包括目标单元和与目标单元相邻的第一相邻单元。 第一目标单元具有连接到地的第一位线; 目标单元还具有连接到感测电路的第二位线。 第一相邻小区与目​​标小区共享第二位线; 在读取操作期间，第一相邻单元还具有连接到感测电路的第三位线。 存储器电路装置在目标单元的读取操作期间以快速和准确的方式导致增加的误差容限。

    Fast, accurate and low power supply voltage booster using A/D converter
    6.
    发明授权
    Fast, accurate and low power supply voltage booster using A/D converter 有权
    使用A / D转换器的快速，准确和低电源电压升压器

    公开(公告)号：US06798275B1

    公开(公告)日：2004-09-28

    申请号：US10406415

    申请日：2003-04-03

    申请人： Binh Quang Le ,  Cathy Thuvan Ly ,  Lee Cleveland ,  Pau-Ling Chen

    发明人： Binh Quang Le ,  Cathy Thuvan Ly ,  Lee Cleveland ,  Pau-Ling Chen

    IPC分类号： G05F110

    CPC分类号： G11C5/145 ,  G11C8/08

    摘要： Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing. The voltage boost circuit is operable to receive the one or more output signals from the supply voltage detection circuit and alter a boost gain of the multi-stage voltage boost circuit based on the one or more output signals, thereby causing the boosted word line voltage to be substantially independent of the supply voltage value.

    摘要翻译： 公开了闪存阵列系统和方法，用于产生用于读取操作的稳压升压字线电压。 该系统包括多级升压电路，其可操作以从电源电压检测电路接收电源电压和一个或多个输出信号，以产生具有大于电源电压的值的升压字线电压。 升压电路包括预充电电路和连接到升压字线的公共节点的多个升压单元以及定时控制电路。 多个升压单元的级级串联耦合，用于级之间的电荷共享，并且将预定数量的升压单元耦合到升压字线公共节点，以在预升压定时期间向升压的字线提供中间电压 从而预期在升压定时期间提供的最后升高的字线电压。 电压升压电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于一个或多个输出信号改变多级升压电路的升压增益，从而使升压的字线电压 基本上不依赖于电源电压值。

    Method and system for detecting defective material surrounding flash memory cells
    7.
    发明授权
    Method and system for detecting defective material surrounding flash memory cells 有权
    用于检测闪存单元周围的有缺陷的材料的方法和系统

    公开(公告)号：US06765827B1

    公开(公告)日：2004-07-20

    申请号：US10384936

    申请日：2003-03-10

    申请人： Jiang Li ,  Lee Cleveland ,  Ming Kwan

    发明人： Jiang Li ,  Lee Cleveland ,  Ming Kwan

    IPC分类号： G11C1606

    CPC分类号： H01L29/66825 ,  G11C16/04 ,  G11C29/50

    摘要： In a method and system for detecting defective material surrounding a flash memory cell, stressing voltage is applied between a control gate and a well of the flash memory cell. A stress recovery process is then performed on the flash memory cell. Any short circuit, formed through the material between the control gate and at least one of drain and source bit line junctions of the flash memory cell, is detected. The material surrounding the flash memory cell may be an inter-level dielectric material. The present invention may be applied to an array of flash memory cells comprising a flash memory device during testing of the flash memory device before being shipped to the customer.

    摘要翻译： 在用于检测闪存单元周围的有缺陷的材料的方法和系统中，在闪存单元的控制栅极和阱之间施加施加电压。 然后在闪存单元上进行应力恢复处理。 检测到通过控制栅极与闪存单元的漏极和源极位线之间的材料形成的任何短路。 围绕闪存单元的材料可以是层间电介质材料。 本发明可以应用于在被发送给客户之前在闪速存储器件的测试期间包括闪存器件的闪存单元的阵列。

    Method of matching core cell and reference cell source resistances
    9.
    发明授权
    Method of matching core cell and reference cell source resistances 有权
    匹配核心单元和参考单元源电阻的方法

    公开(公告)号：US06654285B1

    公开(公告)日：2003-11-25

    申请号：US10083789

    申请日：2002-02-27

    申请人： Richard Fastow ,  Jiang Li ,  Lee Cleveland

    发明人： Richard Fastow ,  Jiang Li ,  Lee Cleveland

    IPC分类号： G11C1134

    CPC分类号： G11C16/28

    摘要： In a method of reading a memory cell of a memory cell array, electrical potentials are applied to a conductive structure connected to the drain, a conductive structure connected to the source, and the gate of the transistor of a cell to be read. Electrical potential are also applied to a conductive structure connected to the drain, a conductive structure connected to the source, and the gate of the transistor of a reference cell, providing current through the reference cell. The level of resistance to current through the reference cell is chosen by selecting the level of resistance in the conductive structure connected to the source of the transistor of the reference cell.

    摘要翻译： 在读取存储单元阵列的存储单元的方法中，将电位施加到连接到漏极的导电结构，连接到源极的导电结构和要读取的单元的晶体管的栅极。 电势也施加到连接到漏极的导电结构，连接到源极的导电结构和参考单元的晶体管的栅极，提供电流通过参考单元。 通过选择连接到参考单元的晶体管的源极的导电结构中的电阻电平来选择通过参考单元的电流的电平。