公开(公告)号：US06885250B1

公开(公告)日：2005-04-26

申请号：US10844116

申请日：2004-05-12

申请人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

发明人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

IPC分类号： G11C7/06 ,  G11C16/24 ,  H03F3/04 ,  G11C16/06 ,  H03F3/45

CPC分类号： G11C16/24 ,  G11C7/067

摘要： A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

摘要翻译： 公开了一种产生快速，稳定和精确的位线电压的共源共栅放大器电路。 根据一个示例性实施例，共射共基放大器电路包括具有连接到位线电压的源极和连接到输出电压的漏极的晶体管。 共源共栅放大器电路还包括具有连接到位线电压的反相输入的差分电路，连接到参考电压的非反相输入以及连接到第一晶体管的栅极的输出。 晶体管和差分电路的工作产生快速，稳定的精确位线电压。

公开(公告)号：US06768679B1

公开(公告)日：2004-07-27

申请号：US10361378

申请日：2003-02-10

申请人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Pauling Chen

发明人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Pauling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/0491 ,  G11C16/24 ,  G11C16/26

摘要： A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.

摘要翻译： 公开了一种用于在存储器读取操作期间感测目标单元中的电流的选择电路。 根据一个实施例，选择电路包括连接到感测电路的感测电路选择器和连接到地的接地选择器。 接地选择器将目标单元的第一位线连接到地，并且感测电路选择器将目标单元的第二位线连接到感测电路。 感测电路选择器还将第一相邻单元的第三位线连接到感测电路。 第一相邻单元与目标单元共享第二位线。

公开(公告)号：US06768677B2

公开(公告)日：2004-07-27

申请号：US10302672

申请日：2002-11-22

申请人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

发明人： Binh Q. Le ,  Lee Cleveland ,  Pauling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/24 ,  G11C7/067

摘要： A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

公开(公告)号：US06731542B1

公开(公告)日：2004-05-04

申请号：US10313444

申请日：2002-12-05

申请人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Chen Pauling

发明人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Chen Pauling

IPC分类号： G11C1606

CPC分类号： G11C16/26 ,  G11C16/0491

摘要： A memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.

摘要翻译： 公开了一种用于在读取操作期间感测目标单元中的电流的存储器电路装置。 根据一个示例性实施例，存储器电路装置包括目标单元和与目标单元相邻的第一相邻单元。 第一目标单元具有连接到地的第一位线; 目标单元还具有连接到感测电路的第二位线。 第一相邻小区与目​​标小区共享第二位线; 在读取操作期间，第一相邻单元还具有连接到感测电路的第三位线。 存储器电路装置在目标单元的读取操作期间以快速和准确的方式导致增加的误差容限。

公开(公告)号：US06967103B2

公开(公告)日：2005-11-22

申请号：US10240902

申请日：2001-05-03

申请人： Paul D. Schwartz ,  George M. Murray ,  O. Manuel Uy ,  Binh Q. Le ,  David D. Scott ,  Ark L. Lew ,  Sharon X. Ling ,  Joseph J. Suter

发明人： Paul D. Schwartz ,  George M. Murray ,  O. Manuel Uy ,  Binh Q. Le ,  David D. Scott ,  Ark L. Lew ,  Sharon X. Ling ,  Joseph J. Suter

IPC分类号： G01N21/64 ,  G01N21/77 ,  G01N33/22

CPC分类号： G01N21/643 ,  G01N21/7703 ,  G01N33/0057 ,  G01N2021/6484 ,  G01N2021/7709 ,  G01N2021/7786 ,  Y10T436/17 ,  Y10T436/170769 ,  Y10T436/173076 ,  Y10T436/173845

摘要： An explosive detector that utilizes an array of molecularly imprinted polymer (MIP) coated, bifurcated fiber optic cables to form an image of a target molecule source. Individual sensor fiber assemblies, each with a calibrated airflow, are used to expose the fibers to the target molecule. The detector energizes a dedicated excitation light source for each fiber, while simultaneously reading and processing the intensity of the resulting fluorescence that is indicative of the concentration of the target molecule. Processing electronics precisely controls the excitation current, and measures the detected signal from each narrow band pass filter and photodiode. A computer with display processes the data to form an image of the target molecule source that can be used to identify the source even when low level contamination of the same molecule is present. The detector can be used to detect multiple and/or non-explosive targets by varying the MIP coating.

摘要翻译： 一种利用分子印迹聚合物（MIP）涂覆的分叉光纤电缆阵列形成靶分子源的图像的爆炸检测器。 使用具有校准气流的各个传感器纤维组件将纤维暴露于靶分子。 检测器为每个纤维激发专用激发光源，同时读取和处理指示靶分子浓度的所得荧光的强度。 处理电子设备精确控制激励电流，并测量来自每个窄带通滤波器和光电二极管的检测信号。 具有显示器的计算机处理数据以形成目标分子源的图像，其即使存在相同分子的低水平污染物也可用于鉴定来源。 检测器可用于通过改变MIP涂层来检测多个和/或非爆炸性靶标。

公开(公告)号：US06608464B1

公开(公告)日：2003-08-19

申请号：US08884714

申请日：1997-06-30

申请人： Ark L. Lew ,  Joseph J. Suter ,  Binh Q. Le

发明人： Ark L. Lew ,  Joseph J. Suter ,  Binh Q. Le

IPC分类号： H07J700

CPC分类号： B60K1/04 ,  B60K16/00 ,  H01M2/1022 ,  H01M2/1066 ,  H01M2/1083 ,  H01M6/5044 ,  H01M10/4257 ,  H01M10/46 ,  H01M10/465 ,  H02J7/025 ,  H02J7/355 ,  H02J50/10

摘要： A self-contained, small, lightweight, portable, renewable, modular integrated power source. The power source consists of a recharging means such as solar cells that are laminated onto a rechargeable energy source such as a solid state polymer battery which in turn is laminated onto a substrate containing circuits which manage the polymer battery charging. Charging of the battery can occur via solar energy or, alternatively, via RF coupling using external RF charging equipment or a hand held generator. For added support, the integrated power source is then bonded to an applications housing or structure. This integrated power source can independently power the electronic application. It can also serve as casing or housing by taking the shape of the application enclosure.

摘要翻译： 独立，小巧，轻便，便携，可再生，模块化的集成电源。 电源由诸如太阳能电池的再充电装置组成，层叠在诸如固态聚合物电池的可再充电能量源上，太阳能电池又被层压到包含管理聚合物电池充电的电路的基板上。 电池的充电可以通过太阳能或者通过使用外部RF充电设备或手持式发电机的RF耦合进行。 为了增加支持，集成电源然后被结合到应用外壳或结构。 该集成电源可以独立为电子应用提供电源。 它还可以通过采取应用程序外壳的形状作为外壳或外壳。

公开(公告)号：US06881593B2

公开(公告)日：2005-04-19

申请号：US10159682

申请日：2002-05-31

申请人： Binh Q. Le ,  Ark L. Lew ,  Harry K. Charles, Jr. ,  Paul D. Schwartz ,  Seppo J. Lehtonen ,  Sharon X. Ling

发明人： Binh Q. Le ,  Ark L. Lew ,  Harry K. Charles, Jr. ,  Paul D. Schwartz ,  Seppo J. Lehtonen ,  Sharon X. Ling

IPC分类号： G01R1/04 ,  G01R31/28 ,  H01L23/498 ,  H01L21/66

CPC分类号： H01L23/49827 ,  G01R1/0416 ,  G01R31/2884 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/4826 ,  H01L2224/48464 ,  H01L2224/48471 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor die adapter assembly includes a semiconductor die cut from a wafer, the die having an active surface including bond pads. A die adapter, also having bond pads, is bonded to the semiconductor die. Die-to-adapter connectors electrically connect the die bond pads to the adapter bond pads. Finally, adapter-to-substrate connectors electrically connect the adapter bond pads to a device substrate. Having bond pads on the die adapter eliminates the need to break and remake the electrical connections to the original bond pads on the die during burn-in testing of the die.

摘要翻译： 半导体管芯适配器组件包括从晶片切割的半导体管芯，该管芯具有包括接合焊盘的活性表面。 还具有接合焊盘的芯片适配器被结合到半导体管芯。 管芯到适配器连接器将管芯接合焊盘电连接到适配器接合焊盘。 最后，适配器到基板连接器将适配器接合焊盘电连接到器件衬底。 在裸片适配器上具有接合垫消除了在裸片的老化测试期间破坏并重新制造与芯片上的原始接合焊盘的电连接的需要。

公开(公告)号：US06493266B1

公开(公告)日：2002-12-10

申请号：US09829193

申请日：2001-04-09

申请人： Santosh K. Yachareni ,  Darlene G. Hamilton ,  Binh Q. Le ,  Kazuhiro Kurihara

发明人： Santosh K. Yachareni ,  Darlene G. Hamilton ,  Binh Q. Le ,  Kazuhiro Kurihara

IPC分类号： G11C1134

CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/3404 ,  G11C16/3436

摘要： A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in association with a dual bit memory cell architecture. The method includes applying one reference voltage signal to the over erased core cell, and a different reference voltage signal to the reference cell, comparing the two currents produced by each, selectively verifying proper soft programming of one or more bits of the cell, determining that the dual bit memory cell is properly soft programmed. The method may also comprise selectively re-verifying proper soft programming of the cells after selectively soft programming at least one or more bits of the cell.

摘要翻译： 公开了用于存储器单元软程序和软程序验证，调整或校正目标最小值与最大值之间的阈值电压的方法和系统，其可以与双位存储器单元架构相关联使用。 该方法包括将一个参考电压信号施加到过擦除的核心单元，以及将不同的参考电压信号施加到参考单元，比较由每个产生的两个电流，选择性地验证单元的一个或多个位的适当的软编程，确定 双位存储单元被正确软编程。 该方法还可以包括在对该小区的至少一个或多个比特进行选择性软编程之后，选择性地重新验证小区的适当的软编程。

公开(公告)号：US6081455A

公开(公告)日：2000-06-27

申请号：US232023

申请日：1999-01-14

申请人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

发明人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/12 ,  G11C16/00

CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/12

摘要： A block decoder includes a p-well. A low voltage source is coupled to the p-well for asserting a body bias voltage to the p-well. An n-type word line pass transistor is positioned within the p-well and is coupled to a word line for passing programming voltages to the word line. A high voltage source is coupled to pass circuitry configured to assert a voltage on a gate of the pass transistor. The low voltage source is configured to apply a voltage of approximately 10 volts or more to the p-well during programming, thus reducing the voltage between the source and body region (and thus the threshold voltage as well) of NMOS transistors disposed within the p-well. Therefore, the amount of voltage needed to be applied to the pass transistors is reduced. Furthermore, the pass circuitry can work for lower supply voltages since the supply voltage is limited by the threshold voltage of the n-type transistors within the p-well.

摘要翻译： 块解码器包括p阱。 低电压源耦合到p阱，用于断定对p阱的体偏置电压。 n型字线传输晶体管位于p阱内并耦合到字线，用于将编程电压传递到字线。 耦合高电压源以通过配置成断定传输晶体管的栅极上的电压的电路。 低电压源被配置为在编程期间向p阱施加大约10伏特或更高的电压，从而降低位于p内的NMOS晶体管的源极和体区之间的电压（以及阈值电压） -好。 因此，需要施加到传输晶体管的电压量减小。 此外，通过电路可以用于较低的电源电压，因为电源电压受p阱内n型晶体管的阈值电压的限制。

公开(公告)号：US5644207A

公开(公告)日：1997-07-01

申请号：US632969

申请日：1996-04-16

申请人： Ark L. Lew ,  Joseph J. Suter ,  Binh Q. Le

发明人： Ark L. Lew ,  Joseph J. Suter ,  Binh Q. Le

IPC分类号： B60K1/04 ,  B60K16/00 ,  H01M2/10 ,  H01M6/50 ,  H01M10/42 ,  H01M10/46 ,  H02J7/02 ,  H02J7/35 ,  H02J7/00

CPC分类号： H01M10/4257 ,  B60K1/04 ,  B60K16/00 ,  H01M10/46 ,  H01M10/465 ,  H01M2/1022 ,  H01M2/1066 ,  H01M2/1083 ,  H02J7/025 ,  H02J7/355 ,  H01M6/5044 ,  Y02B10/14 ,  Y02T10/90 ,  Y10T307/50

摘要： A self-contained, small, lightweight, portable, renewable, modular integrated power source. The power source consists of solar cells that are laminated onto a solid state polymer battery which in turn is laminated onto a substrate containing circuits which manage the polymer battery charging. Charging of the battery can occur via solar energy or, alternatively, via RF coupling using external RF charging equipment or a hand held generator. For added support, the integrated power source is then bonded to an applications housing or structure. This integrated power source can independently power the electronic application. It can also serve as casing or housing by taking the shape of the application enclosure.

摘要翻译： 独立，小巧，轻便，便携，可再生，模块化的集成电源。 电源由层叠在固体聚合物电池上的太阳能电池组成，而固体聚合物电池又被层压到含有管理聚合物电池充电的电路的基板上。 电池的充电可以通过太阳能或者通过使用外部RF充电设备或手持式发电机的RF耦合进行。 为了增加支持，集成电源然后被结合到应用外壳或结构。 该集成电源可以独立为电子应用提供电源。 它还可以通过采取应用程序外壳的形状作为外壳或外壳。