公开(公告)号：US06768679B1

公开(公告)日：2004-07-27

申请号：US10361378

申请日：2003-02-10

申请人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Pauling Chen

发明人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Pauling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/0491 ,  G11C16/24 ,  G11C16/26

摘要： A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.

摘要翻译： 公开了一种用于在存储器读取操作期间感测目标单元中的电流的选择电路。 根据一个实施例，选择电路包括连接到感测电路的感测电路选择器和连接到地的接地选择器。 接地选择器将目标单元的第一位线连接到地，并且感测电路选择器将目标单元的第二位线连接到感测电路。 感测电路选择器还将第一相邻单元的第三位线连接到感测电路。 第一相邻单元与目标单元共享第二位线。

公开(公告)号：US06731542B1

公开(公告)日：2004-05-04

申请号：US10313444

申请日：2002-12-05

申请人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Chen Pauling

发明人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Chen Pauling

IPC分类号： G11C1606

CPC分类号： G11C16/26 ,  G11C16/0491

摘要： A memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.

摘要翻译： 公开了一种用于在读取操作期间感测目标单元中的电流的存储器电路装置。 根据一个示例性实施例，存储器电路装置包括目标单元和与目标单元相邻的第一相邻单元。 第一目标单元具有连接到地的第一位线; 目标单元还具有连接到感测电路的第二位线。 第一相邻小区与目​​标小区共享第二位线; 在读取操作期间，第一相邻单元还具有连接到感测电路的第三位线。 存储器电路装置在目标单元的读取操作期间以快速和准确的方式导致增加的误差容限。

公开(公告)号：US07894267B2

公开(公告)日：2011-02-22

申请号：US11929741

申请日：2007-10-30

申请人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

发明人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/12

摘要： Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.

摘要翻译： 改进存储器件编程的系统和方法。 脉冲分量将不同的编程脉冲施加到存储单元。 分析组件根据应用的不同编程脉冲测量存储器单元的一个或多个特性的值。 计算组件根据存储单元的一个或多个特性的测量值来计算应用的不同编程脉冲。 分析组件测量存储器单元的一个或多个特性的一个或多个值，计算组件根据存储器单元的一个或多个特性的一个或多个测量值来计算一个或多个编程脉冲，以及 脉冲分量将一个或多个编程脉冲施加到存储器单元。

公开(公告)号：US07835189B2

公开(公告)日：2010-11-16

申请号：US11687492

申请日：2007-03-16

申请人： Michael Achter ,  Hagop Nazarian

发明人： Michael Achter ,  Hagop Nazarian

IPC分类号： G11C16/06

CPC分类号： G11C16/10

摘要： Flash memory devices have a plurality of memory cells that can be erased and programmed. Performing a voltage verification check allows a for an appropriate state-change voltage to be applied to the flash memory device. The appropriate state-change voltage is determined though accessing a look-up table. Using an appropriate state-change voltage allows a cell to operate with more overall programming cycles.

摘要翻译： 闪存设备具有可被擦除和编程的多个存储器单元。 执行电压验证检查允许将适当的状态变化电压施加到闪存器件。 通过访问查找表来确定适当的状态变化电压。 使用适当的状态变化电压允许电池在更多的总体编程周期下运行。

公开(公告)号：US20100037032A1

公开(公告)日：2010-02-11

申请号：US12189746

申请日：2008-08-11

申请人： Michael Achter

发明人： Michael Achter

IPC分类号： G06F12/00

CPC分类号： G11C16/3427 ,  G11C11/5628

摘要： Providing systems and methods that reduce memory device read errors and improve memory device reliability by intelligently disturbing the memory cells during storage of their characteristic states. A specification component can determine a desired characteristic state for each cell of a plurality of multi-cell memory devices. A storage component can, alternatively, successively store an equivalent characteristic state in each cell of the plurality of multi-cell memory devices in stages, based on a cell's current characteristic state, or directly store the desired characteristic state of each cell of the plurality of multi-cell memory devices, based on an ordering of desired characteristic states of cells of the multi-cell memory devices. Further, a step component can gradate the equivalent characteristic state between successive storage stages. In this way, the overlap of distributions of electrical characteristics associated with different bits of one or more memory cells can be reduced.

摘要翻译： 提供减少存储器读取错误并通过在存储器特征状态存储期间智能地干扰存储器单元来提高存储器件可靠性的系统和方法。 规范组件可以确定多个多小区存储设备中的每个小区的期望特征状态。 或者，存储组件可以基于小区的当前特性状态，分级地依次存储多个多小区存储设备的每个小区中的等效特征状态，或者直接存储多个小区的每个小区的期望特征状态 多单元存储器件，基于多单元存储器件的单元的期望特性状态的排序。 此外，步进部件可以逐渐降级连续的存储阶段之间的等效特征状态。 以这种方式，可以减少与一个或多个存储器单元的不同位相关联的电特性的分布的重叠。

公开(公告)号：US20090154261A1

公开(公告)日：2009-06-18

申请号：US11955802

申请日：2007-12-13

申请人： Michael Achter

发明人： Michael Achter

IPC分类号： G11C7/00

CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C7/062 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/344 ,  G11C16/3454

摘要： Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the applied plurality of different stimuli. An analysis component determines a logic state of each memory cell of the plurality of memory cells as a function of the sensed characteristic of each memory cell of the plurality of memory cells.

摘要翻译： 通过利用无参考采样传感来延长存储器单元的使用寿命的系统和方法。 刺激分量将多个不同的刺激应用于存储器件的多个存储器单元。 感测组件根据应用的多个不同的刺激来感测多个存储器单元中的每个存储器单元的特性。 分析组件根据多个存储器单元中每个存储器单元的感测特性来确定多个存储器单元中的每个存储器单元的逻辑状态。

公开(公告)号：US20100142284A1

公开(公告)日：2010-06-10

申请号：US12330928

申请日：2008-12-09

申请人： Fatima Bathul ,  Darlene Gay Hamilton ,  Michael Achter ,  Hagop Artin Nazarian

发明人： Fatima Bathul ,  Darlene Gay Hamilton ,  Michael Achter ,  Hagop Artin Nazarian

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/04

摘要： Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt.

摘要翻译： 提出了使用确定性编程技术来促进存储器中的存储器元件的有效编程的系统，方法和设备。 存储器组件包括优化的程序组件，其可以部分地基于存储器元件的相应电流阈值电压电平（Vt）将被选择用于编程的一组存储器元件划分为期望数量的子组; 将相应的编程脉冲施加到各个子组中的每个存储元件; 在脉冲之后测量存储元件的各个Vt电平; 并且验证为满足目标Vt的传递的存储器元件。优化的程序组件可以部分地基于存储器元件的相应的当前Vt级别将不满足目标Vt的存储器元件的子集划分为期望数量的子组，并且可以 继续执行此确定性编程过程，直到所有存储器元素被验证为传递目标Vt为止。

公开(公告)号：US07567457B2

公开(公告)日：2009-07-28

申请号：US11929724

申请日：2007-10-30

申请人： Hagop Nazarian ,  Harry Kuo ,  Michael Achter

发明人： Hagop Nazarian ,  Harry Kuo ,  Michael Achter

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC分类号： G11C8/14 ,  G11C8/08 ,  G11C16/0416 ,  G11C16/0491 ,  G11C16/10

摘要： An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.

摘要翻译： 一种包括多对非易失性存储器（“NVM”）单元的二维或三维阵列的装置，其被耦合以使能NVM单元的编程和擦除。 多对NVM单元电连接到字线和位线。 每对NVM单元包括第一存储单元和第二存储单元。 第一和第二存储单元包括第一源极/漏极，第二源极/漏极和控制栅极。 第一存储单元的第一源极/漏极连接到位线之一。 第一存储单元的第二源极/漏极连接到第二存储单元的第一源极/漏极。 第二存储单元的第二源极/漏极连接到另一个位线。 第一和第二存储单元的控制栅极连接到不同的字线。

公开(公告)号：US07498849B2

公开(公告)日：2009-03-03

申请号：US11985427

申请日：2007-11-15

申请人： Takao Akaogi ,  Sameer Wadhwa ,  Michael Achter ,  Bhimachar Venkatesh

发明人： Takao Akaogi ,  Sameer Wadhwa ,  Michael Achter ,  Bhimachar Venkatesh

IPC分类号： G01R19/00 ,  G11C7/00

CPC分类号： G11C7/062 ,  G11C2207/063 ,  H03F3/345 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/462 ,  H03F2200/78

摘要： A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

摘要翻译： 读出放大器包括用于产生参考输出电压的参考电压发生器和用于产生核心输出电压的核心输出电压发生器。 核心输出电压发生器包括核心前端级和核心后端级，或者包括多个放大器晶体管，每个放大器晶体管通过诸如核心单元之类的电流传导器件导通核心电流的一部分。 这种组件的晶体管的尺寸和/或连接导致高电压摆动，从而导致读出放大器的高灵敏度。

公开(公告)号：US20080229122A1

公开(公告)日：2008-09-18

申请号：US11687487

申请日：2007-03-16

申请人： Michael Achter

发明人： Michael Achter

IPC分类号： G06F1/00

CPC分类号： G06F1/28

摘要： Application of too much voltage to a memory cell will cause damage to the cell or even destroy the cell. Tracking current that arises from an application of voltage upon a memory cell allows for minimization of damage upon the memory cell. If there is a change in current, then the voltage application can be accordingly changed.

摘要翻译： 对存储器单元施加过大的电压将导致电池损坏甚至破坏电池。 由于在存储单元上施加电压引起的跟踪电流允许最小化对存储单元的损坏。 如果电流有变化，则可以相应地改变电压施加。