公开(公告)号：US06798275B1

公开(公告)日：2004-09-28

申请号：US10406415

申请日：2003-04-03

申请人： Binh Quang Le ,  Cathy Thuvan Ly ,  Lee Cleveland ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Cathy Thuvan Ly ,  Lee Cleveland ,  Pau-Ling Chen

IPC分类号： G05F110

CPC分类号： G11C5/145 ,  G11C8/08

摘要： Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing. The voltage boost circuit is operable to receive the one or more output signals from the supply voltage detection circuit and alter a boost gain of the multi-stage voltage boost circuit based on the one or more output signals, thereby causing the boosted word line voltage to be substantially independent of the supply voltage value.

摘要翻译： 公开了闪存阵列系统和方法，用于产生用于读取操作的稳压升压字线电压。 该系统包括多级升压电路，其可操作以从电源电压检测电路接收电源电压和一个或多个输出信号，以产生具有大于电源电压的值的升压字线电压。 升压电路包括预充电电路和连接到升压字线的公共节点的多个升压单元以及定时控制电路。 多个升压单元的级级串联耦合，用于级之间的电荷共享，并且将预定数量的升压单元耦合到升压字线公共节点，以在预升压定时期间向升压的字线提供中间电压 从而预期在升压定时期间提供的最后升高的字线电压。 电压升压电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于一个或多个输出信号改变多级升压电路的升压增益，从而使升压的字线电压 基本上不依赖于电源电压值。

公开(公告)号：US06894473B1

公开(公告)日：2005-05-17

申请号：US10379744

申请日：2003-03-05

申请人： Binh Quang Le ,  Cathy Thuvan Ly ,  Lee Cleveland ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Cathy Thuvan Ly ,  Lee Cleveland ,  Pau-Ling Chen

IPC分类号： G05F3/16 ,  G05F3/30

CPC分类号： G05F3/30

摘要： A bandgap reference circuit includes a current generation circuit connected to a voltage generation circuit connected to a smart clamping circuit, and a discharge circuit connected to the current generation circuit and the voltage generation circuit. The discharge circuit initially discharges a potential in the current and voltage generation circuits to improve repeatability. A start circuit within the current generation circuit then initializes the reference output at about the supply voltage to improve the speed and settling time of the output signal. The current generation circuit sources a current to the voltage generation circuit that translates the current having a positive function of temperature +TC into a reference voltage. The smart clamping circuit further generates a clamping voltage having a negative function of temperature −TC and a load resistance. The clamping voltage and the load resistance are applied across the reference voltage quickly reducing the reference voltage particularly at high temperatures and during start-up to a final level, thereby producing a fast and stable reference voltage.

摘要翻译： 带隙基准电路包括与连接到智能钳位电路的电压产生电路连接的电流产生电路和连接到电流产生电路和电压产生电路的放电电路。 放电电路最初在电流和电压产生电路中释放电位以改善重复性。 然后，当前发电电路中的启动电路在大约电源电压下初始化参考输出，以提高输出信号的速度和稳定时间。 电流产生电路将电流输出到电压产生电路，其将具有温度+ T C C的正函数的电流转换为参考电压。 智能钳位电路进一步产生具有温度-T T C的负功能和负载电阻的钳位电压。 钳位电压和负载电阻跨越参考电压施加，特别是在高温下和启动期间快速降低参考电压，从而产生快速稳定的参考电压。

公开(公告)号：US06781417B1

公开(公告)日：2004-08-24

申请号：US10282459

申请日：2002-10-29

申请人： Binh Quang Le ,  Lee Cleveland ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Lee Cleveland ,  Pau-Ling Chen

IPC分类号： H03K19185

CPC分类号： G05F3/242 ,  H03K19/018507

摘要： According to one exemplary embodiment, a buffer circuit is configured to receive a supply voltage and an input reference voltage, the buffer circuit has a first FET operating in saturation region where the source of the first FET is coupled to the output reference voltage. The first FET can be configured, for example, as an open-loop voltage follower and, by way of example, a first resistor can be used to couple the source of the first FET to the output reference voltage. A tracking circuit is connected to the buffer circuit. The tracking circuit comprises a second FET also operating in saturation region where the drain of the second FET is coupled to the output reference voltage. Both the first and second FETs can be, for example, depletion mode transistors.

摘要翻译： 根据一个示例性实施例，缓冲电路被配置为接收电源电压和输入参考电压，所述缓冲电路具有在饱和区域中工作的第一FET，其中第一FET的源极耦合到输出参考电压。 第一FET可以被配置为例如开环电压跟随器，并且作为示例，可以使用第一电阻器将第一FET的源极耦合到输出参考电压。 跟踪电路连接到缓冲电路。 跟踪电路包括也在饱和区域工作的第二FET，其中第二FET的漏极耦合到输出参考电压。 第一和第二FET都可以是例如耗尽型晶体管。

公开(公告)号：US06791880B1

公开(公告)日：2004-09-14

申请号：US10431320

申请日：2003-05-06

申请人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

发明人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

IPC分类号： G11C1606

CPC分类号： G11C29/026 ,  G11C16/04 ,  G11C16/349 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006

摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.

摘要翻译： 具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。 包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源 参考电流源。 来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。 可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流 或骑自行车。

公开(公告)号：US06643177B1

公开(公告)日：2003-11-04

申请号：US10349293

申请日：2003-01-21

申请人： Binh Quang Le ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Pau-Ling Chen

IPC分类号： G11C1628

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/28 ,  G11C2211/5634

摘要： A method for providing a modified threshold voltage distribution for a dynamic reference array in a flash memory cell array. The dynamic reference array and an associated core memory cell array are programmed using two different programming processes to produce different Vt distributions for the dynamic reference array and the core memory cell array. The dynamic reference array is programmed using a finer program pulse to achieve a smaller distribution width, thus enhancing the read margin for the memory cell array. The finer pulse may be of shorter duration or of smaller amplitude. The finer programming process may be applied to one or more threshold voltage distributions (states) in the memory cell array.

摘要翻译： 一种用于为闪存单元阵列中的动态参考阵列提供修改的阈值电压分布的方法。 使用两个不同的编程过程对动态参考阵列和相关联的核心存储器单元阵列进行编程，以为动态参考阵列和核心存储器单元阵列产生不同的Vt分布。 使用更精细的编程脉冲对动态参考阵列进行编程，以实现更小的分布宽度，从而增强存储单元阵列的读取余量。 较细的脉冲可以具有较短的持续时间或较小的振幅。 更精细的编程过程可以应用于存储单元阵列中的一个或多个阈值电压分布（状态）。

公开(公告)号：US06269025B1

公开(公告)日：2001-07-31

申请号：US09500699

申请日：2000-02-09

申请人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-Ling Chen

发明人： Shane C. Hollmer ,  Binh Quang Le ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： G11C5/147 ,  G11C16/12 ,  G11C16/16

摘要： A memory system has the capability to adjust a program or erase voltage if the time to program or erase is excessive. The memory system comprises at least a memory cell, a voltage value storage device, a voltage source, and a voltage adjustment circuit. The voltage value storage device stores a voltage value. The voltage source receives and converts the voltage value into a voltage. The voltage source applies the voltage to at least one memory cell. The voltage adjustment circuit is also coupled to receive the stored voltage value. The voltage adjustment circuit determines the time required to program or erase at least one memory cell using the voltage value. If the time to program or erase at least one memory cell is excessive, the voltage adjustment circuit increments the voltage value stored in the voltage value storage device.

摘要翻译： 如果编程或擦除时间过长，存储系统可以调整程序或擦除电压。 存储器系统至少包括存储器单元，电压值存储器件，电压源和电压调节电路。 电压值存储装置存储电压值。 电压源接收并将电压值转换为电压。 电压源将电压施加到至少一个存储单元。 电压调节电路也耦合以接收存储的电压值。 电压调节电路使用电压值来确定编程或擦除至少一个存储单元所需的时间。 如果编程或擦除至少一个存储单元的时间过长，则电压调节电路增加存储在电压值存储装置中的电压值。

公开(公告)号：US5844840A

公开(公告)日：1998-12-01

申请号：US914543

申请日：1997-08-19

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Chung-You Hu ,  Narbeh Derhacobian

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Chung-You Hu ,  Narbeh Derhacobian

IPC分类号： G11C8/08 ,  G11C16/06

CPC分类号： G11C8/08

摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.

摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

公开(公告)号：US07076703B1

公开(公告)日：2006-07-11

申请号：US10305700

申请日：2002-11-26

申请人： Binh Quang Le ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Pau-Ling Chen

IPC分类号： G11C29/00

CPC分类号： G11C29/804

摘要： A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.

摘要翻译： 一种用于存储器冗余的方法，包括通常具有存储器单元的多个列（例如，位线）的存储器阵列，以及识别存储器阵列的特定（例如，有缺陷的）列，并进一步通过选择一个 一组相邻列，包括有缺陷的列。 所选列组中的列数可以等于耦合到存储器阵列的冗余阵列中的列数。 冗余阵列用于存储否则将存储在冗余窗口中的存储器单元中的信息。 所选择的组包括在缺陷列的一侧上的至少一个列和在缺陷列的另一侧上的另一个列。 通常，有缺陷的列的每一侧将有多个列。

公开(公告)号：US06288951B1

公开(公告)日：2001-09-11

申请号：US09675940

申请日：2000-09-29

申请人： Pau-Ling Chen ,  Binh Quang Le

发明人： Pau-Ling Chen ,  Binh Quang Le

IPC分类号： G11C700

CPC分类号： G11C5/145

摘要： A non-volatile memory and method for continuously regulating an output of a charge pump of the non-volatile memory for long periods of time at a target output voltage.

摘要翻译： 一种非易失性存储器和方法，用于在目标输出电压下长时间持续地调节非易失性存储器的电荷泵的输出。

公开(公告)号：US06262469B1

公开(公告)日：2001-07-17

申请号：US09047237

申请日：1998-03-25

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

IPC分类号： H01L2900

CPC分类号： H01L29/94 ,  H01L27/0811 ,  H01L29/66189

摘要： A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.

摘要翻译： 电容器分压器包括两个电容器，它们串联在两个电压源之间。 第一电容器是浮置栅极电容器，其中一个板是浮栅晶体管结构的控制栅极，另一个栅极是浮栅晶体管结构的源极，漏极和沟道区。 电容分压器的优点是具有至少一个浮置栅极电容器，可以在电压调节器中实现，并且可以用于跨越电容器的各种电压。