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公开(公告)号：US06269025B1
公开(公告)日：2001-07-31
申请号：US09500699
申请日：2000-02-09
申请人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
发明人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C1604
摘要： A memory system has the capability to adjust a program or erase voltage if the time to program or erase is excessive. The memory system comprises at least a memory cell, a voltage value storage device, a voltage source, and a voltage adjustment circuit. The voltage value storage device stores a voltage value. The voltage source receives and converts the voltage value into a voltage. The voltage source applies the voltage to at least one memory cell. The voltage adjustment circuit is also coupled to receive the stored voltage value. The voltage adjustment circuit determines the time required to program or erase at least one memory cell using the voltage value. If the time to program or erase at least one memory cell is excessive, the voltage adjustment circuit increments the voltage value stored in the voltage value storage device.
摘要翻译： 如果编程或擦除时间过长，存储系统可以调整程序或擦除电压。 存储器系统至少包括存储器单元，电压值存储器件，电压源和电压调节电路。 电压值存储装置存储电压值。 电压源接收并将电压值转换为电压。 电压源将电压施加到至少一个存储单元。 电压调节电路也耦合以接收存储的电压值。 电压调节电路使用电压值来确定编程或擦除至少一个存储单元所需的时间。 如果编程或擦除至少一个存储单元的时间过长，则电压调节电路增加存储在电压值存储装置中的电压值。
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公开(公告)号：US6005804A
公开(公告)日：1999-12-21
申请号：US993634
申请日：1997-12-18
申请人： Shane C. Hollmer , Binh Quang Le , Pau-ling Chen
发明人： Shane C. Hollmer , Binh Quang Le , Pau-ling Chen
CPC分类号： G11C16/0483 , G11C16/10
摘要： An EEPROM NAND array has floating gate memory cells coupled in series, each having a control gate, a floating gate, a body region, and an insulating layer between the floating gate and the body region. A negative charge pump is coupled to the body region. In programming, the body region of the memory cell selected for programming is biased to a negative voltage by the negative charge pump while the control gate of the memory cell is biased to a predetermined positive voltage sufficient to induce Fowler-Nordheim tunneling from the body region into the floating gate. The present invention allows the programming voltage requirement at the control gate of a NAND EEPROM memory cell to be significantly reduced which allows for the peripheral voltage delivery circuitry in NAND EEPROM arrays to be designed for lower voltages than for conventional NAND EEPROM arrays.
摘要翻译： EEPROM NAND阵列具有串联耦合的浮动栅极存储单元，每个浮动栅极存储单元在浮置栅极和体区之间具有控制栅极，浮动栅极，体区域和绝缘层。 负电荷泵耦合到身体区域。 在编程中，选择用于编程的存储单元的主体区域被负电荷泵偏置到负电压，而存储单元的控制栅极被偏置到预定的正电压以足以引导来自身体区域的Fowler-Nordheim隧穿 进入浮动门。 本发明允许NAND EEPROM存储单元的控制栅极上的编程电压要求显着降低，这允许NAND EEPROM阵列中的外围电压传送电路被设计为比传统的NAND EEPROM阵列更低的电压。
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3.发明授权
公开(公告)号：US5995417A
公开(公告)日：1999-11-30
申请号：US175646
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
发明人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.
摘要翻译： 非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页 被擦除和擦除验证。 擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他 连接到未选择用于页面擦除的字线的MOS晶体管。 在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。
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4.发明授权Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same 有权位线偏置方法，用于消除非易失性存储器件和采用其中的存储器件中的程序干扰
公开(公告)号：US5978267A
公开(公告)日：1999-11-02
申请号：US175647
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael Van Buskirk , Shane C. Hollmer , Michael S. C. Chung , Binh Quang Le , Vincent Leung , Shoichi Kawamura , Masaru Yano
发明人： Pau-Ling Chen , Michael Van Buskirk , Shane C. Hollmer , Michael S. C. Chung , Binh Quang Le , Vincent Leung , Shoichi Kawamura , Masaru Yano
CPC分类号： G11C16/10 , G11C16/0483 , G11C7/12
摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.
摘要翻译： 在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。 在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。
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5.发明授权Method and apparatus for adjusting on-chip current reference for EEPROM sensing 有权用于调整EEPROM感应的片内电流参考的方法和装置公开(公告)号：US06525966B1
公开(公告)日：2003-02-25
申请号：US10010985
申请日：2001-12-05
IPC分类号： G11C1606
摘要： Method and apparatus for a memory circuit having a sense amplifier circuit having a sensing amplifier connected to read the data content output of a memory cell where the sense amplifier circuit includes a current source transistor having a gate terminal and having a drain terminal connected to a voltage supply and having a source terminal connected to the sensing amplifier, with a selectable source current in order to account for variation from a desired source current due to variations in the designed source current transistor performance parameters.
摘要翻译： 一种具有读出放大器电路的存储电路的方法和装置，该读出放大器电路具有连接到读出存储单元的数据内容输出的感测放大器，其中读出放大器电路包括具有栅极端子并具有连接到电压的漏极端子的电流源晶体管 提供并具有连接到感测放大器的源极端子，具有可选择的源极电流，以便考虑到由于设计的源极电流晶体管性能参数的变化而导致的期望源极电流的变化。
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公开(公告)号：US06791880B1
公开(公告)日：2004-09-14
申请号：US10431320
申请日：2003-05-06
IPC分类号： G11C1606
CPC分类号： G11C29/026 , G11C16/04 , G11C16/349 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C2029/5006
摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.
摘要翻译： 具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。 包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源 参考电流源。 来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。 可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流 或骑自行车。
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公开(公告)号：US06643177B1
公开(公告)日：2003-11-04
申请号：US10349293
申请日：2003-01-21
申请人： Binh Quang Le , Pau-Ling Chen
发明人： Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C1628
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0475 , G11C16/28 , G11C2211/5634
摘要： A method for providing a modified threshold voltage distribution for a dynamic reference array in a flash memory cell array. The dynamic reference array and an associated core memory cell array are programmed using two different programming processes to produce different Vt distributions for the dynamic reference array and the core memory cell array. The dynamic reference array is programmed using a finer program pulse to achieve a smaller distribution width, thus enhancing the read margin for the memory cell array. The finer pulse may be of shorter duration or of smaller amplitude. The finer programming process may be applied to one or more threshold voltage distributions (states) in the memory cell array.
摘要翻译： 一种用于为闪存单元阵列中的动态参考阵列提供修改的阈值电压分布的方法。 使用两个不同的编程过程对动态参考阵列和相关联的核心存储器单元阵列进行编程，以为动态参考阵列和核心存储器单元阵列产生不同的Vt分布。 使用更精细的编程脉冲对动态参考阵列进行编程，以实现更小的分布宽度，从而增强存储单元阵列的读取余量。 较细的脉冲可以具有较短的持续时间或较小的振幅。 更精细的编程过程可以应用于存储单元阵列中的一个或多个阈值电压分布（状态）。
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8.发明授权High voltage NMOS pass gate having supply range, area, and speed advantages 失效具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5844840A
公开(公告)日：1998-12-01
申请号：US914543
申请日：1997-08-19
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。
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9.发明授权Fast, accurate and low power supply voltage booster using A/D converter 有权使用A / D转换器的快速，准确和低电源电压升压器公开(公告)号：US06798275B1
公开(公告)日：2004-09-28
申请号：US10406415
申请日：2003-04-03
申请人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
发明人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
IPC分类号： G05F110
摘要： Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing. The voltage boost circuit is operable to receive the one or more output signals from the supply voltage detection circuit and alter a boost gain of the multi-stage voltage boost circuit based on the one or more output signals, thereby causing the boosted word line voltage to be substantially independent of the supply voltage value.
摘要翻译： 公开了闪存阵列系统和方法，用于产生用于读取操作的稳压升压字线电压。 该系统包括多级升压电路，其可操作以从电源电压检测电路接收电源电压和一个或多个输出信号，以产生具有大于电源电压的值的升压字线电压。 升压电路包括预充电电路和连接到升压字线的公共节点的多个升压单元以及定时控制电路。 多个升压单元的级级串联耦合，用于级之间的电荷共享，并且将预定数量的升压单元耦合到升压字线公共节点，以在预升压定时期间向升压的字线提供中间电压 从而预期在升压定时期间提供的最后升高的字线电压。 电压升压电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于一个或多个输出信号改变多级升压电路的升压增益，从而使升压的字线电压 基本上不依赖于电源电压值。
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公开(公告)号：US06304487B1
公开(公告)日：2001-10-16
申请号：US09514404
申请日：2000-02-28
IPC分类号： G11C1606
CPC分类号： G11C16/12 , G11C16/10 , G11C16/3436
摘要： A voltage control circuit that programs or erases memory cells comprises an internal voltage value store, a register device selectively coupled to an external voltage value source or the internal voltage value store to receive a voltage value, a voltage output circuit coupled to the register device to receive the voltage value and to output a corresponding voltage to the memory cells, and a verify circuit determining the time to successfully program or erase the memory cells. The register device allows the memory cells to be programmed or erased with voltage values designated by the external voltage value source to determine programming and erasing characteristics of the memory cells. Voltage values producing acceptable programming and erasing characteristics are saved in the internal voltage value store.
摘要翻译： 编程或擦除存储器单元的电压控制电路包括内部电压值存储器，选择性地耦合到外部电压值源的寄存器器件或用于接收电压值的内部电压值存储器，耦合到寄存器器件的电压输出电路， 接收电压值并将相应的电压输出到存储器单元，以及确认电路确定成功编程或擦除存储单元的时间。 寄存器件允许用由外部电压值源指定的电压值对存储器单元进行编程或擦除，以确定存储器单元的编程和擦除特性。 产生可接受的编程和擦除特性的电压值被保存在内部电压值存储器中。
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