公开(公告)号：US20160315018A1

公开(公告)日：2016-10-27

申请号：US15167050

申请日：2016-05-27

申请人： Bok-Young LEE ,  Jeong-Yun LEE ,  Dong-Hyun KIM ,  Myeong-Cheol KIM ,  Dong-Woo HAN

发明人： Bok-Young LEE ,  Jeong-Yun LEE ,  Dong-Hyun KIM ,  Myeong-Cheol KIM ,  Dong-Woo HAN

IPC分类号： H01L21/8238 ,  H01L21/306 ,  H01L29/66

CPC分类号： H01L21/823821 ,  H01L21/30604 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795

摘要： Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括从衬底突出并沿第一方向延伸的第一有源鳍片和第二有源鳍片，第一栅极结构，其在第一有源鳍片上沿着与第一方向相交的第二方向延伸;第二栅极 结构，其位于第二方向上与第一栅极结构相邻并且在第二有源鳍上沿着第二方向延伸;以及虚设结构，其位于第一栅极结构和第二栅极结构之间的空间中。

公开(公告)号：US20080203590A1

公开(公告)日：2008-08-28

申请号：US12111651

申请日：2008-04-29

申请人： Chang-Jin KANG ,  Myeong-Cheol KIM ,  Man-Hyoung RYOO ,  Si-Hyeung LEE ,  Doo-Youl LEE

发明人： Chang-Jin KANG ,  Myeong-Cheol KIM ,  Man-Hyoung RYOO ,  Si-Hyeung LEE ,  Doo-Youl LEE

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

摘要翻译： 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US20150097251A1

公开(公告)日：2015-04-09

申请号：US14569597

申请日：2014-12-12

申请人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

发明人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。