公开(公告)号：US20090102017A1

公开(公告)日：2009-04-23

申请号：US12247315

申请日：2008-10-08

Applicant: Yong-kug BAE ,  Si-hyeung LEE ,  Tae-hyuk AHN ,  Seok-hwan OH

Inventor： Yong-kug BAE ,  Si-hyeung LEE ,  Tae-hyuk AHN ,  Seok-hwan OH

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L28/91

Abstract: A semiconductor device and a method of fabricating a semiconductor device provide high quality cylindrical capacitors. The semiconductor device includes a substrate defining a cell region and a peripheral circuit region, a plurality of capacitors in the cell region, and supports for supporting lower electrodes of the capacitors. The lower electrodes are disposed in a plurality of rows each extending in a first direction. A dielectric layer is disposed on the lower electrodes, and an upper electrode is disposed on the dielectric layer. The supports are in the form of stripes extending longitudinally in the first direction and spaced from each other along a second direction. Each of the supports engages the lower electrodes of a respective plurality of adjacent rows of the lower electrodes. Each one of the supports is also disposed at a different level in the device from the support that is adjacent thereto in the second direction.

Abstract translation: 半导体器件和制造半导体器件的方法提供高质量的圆柱形电容器。 半导体器件包括限定单元区域和外围电路区域的基板，单元区域中的多个电容器以及用于支撑电容器的下部电极的支撑。 下电极配置成沿着第一方向延伸的多列。 电介质层设置在下电极上，上电极设置在电介质层上。 支撑体是沿着第一方向纵向延伸并且沿着第二方向彼此间隔开的条纹的形式。 每个支撑件接合下电极的相应多个相邻行的下电极。 每个支撑件还设置在与第二方向相邻的支撑件处于装置中的不同水平处。

公开(公告)号：US07241552B2

公开(公告)日：2007-07-10

申请号：US10909384

申请日：2004-08-03

Applicant: Kwang-sub Yoon ,  Dong-won Jung ,  Si-hyeung Lee ,  Hyun-woo Kim ,  Sook Lee ,  Sang-gyun Woo ,  Sang-jun Choi

Inventor： Kwang-sub Yoon ,  Dong-won Jung ,  Si-hyeung Lee ,  Hyun-woo Kim ,  Sook Lee ,  Sang-gyun Woo ,  Sang-jun Choi

IPC: G03F7/004

CPC classification number: G03F7/0395 ,  G03F7/0392 ,  G03F7/0397 ,  Y10S430/106

Abstract: A resist composition includes a photoacid generator (PAG) and a photosensitive polymer. The photosensitive polymer is polymerized with (a) at least one of the monomers having the respective formulae: where R1 and R2 are independently a hydrogen atom, alkyl, hydroxyalkyl, alkyloxy, carbonyl or ester, and x and y are independently integers from 1 to 6, and (b) at least one of a (meth)acrylate monomer, a maleic anhydride monomer, and a norbornene monomer.

Abstract translation: 抗蚀剂组合物包括光致酸产生剂（PAG）和光敏聚合物。 光敏聚合物与（a）至少一种具有以下各式的单体聚合：其中R 1和R 2独立地为氢原子，烷基，羟基烷基，烷氧基，羰基或酯，x和y独立地为1至 6，和（b）至少一种（甲基）丙烯酸酯单体，马来酸酐单体和降冰片烯单体。

公开(公告)号：US20050008975A1

公开(公告)日：2005-01-13

申请号：US10909384

申请日：2004-08-03

Applicant: Kwang-sub Yoon ,  Dong-won Jung ,  Si-hyeung Lee ,  Hyun-woo Kim ,  Sook Lee ,  Sang-gyun Woo ,  Sang-jun Choi

Inventor： Kwang-sub Yoon ,  Dong-won Jung ,  Si-hyeung Lee ,  Hyun-woo Kim ,  Sook Lee ,  Sang-gyun Woo ,  Sang-jun Choi

IPC: C08F220/18 ,  C08F222/06 ,  C08F232/04 ,  C08F234/02 ,  G03F7/004 ,  G03F7/039 ,  H01L21/027 ,  G03C1/76

CPC classification number: G03F7/0395 ,  G03F7/0392 ,  G03F7/0397 ,  Y10S430/106

Abstract: A resist composition includes a photoacid generator (PAG) and a photosensitive polymer. The photosensitive polymer is polymerized with (a) at least one of the monomers having the respective formulae: where R1 and R2 are independently a hydrogen atom, alkyl, hydroxyalkyl, alkyloxy, carbonyl or ester, and x and y are independently integers from 1 to 6, and (b) at least one of a (meth)acrylate monomer, a maleic anhydride monomer, and a norbornene monomer.

Abstract translation: 抗蚀剂组合物包括光致酸产生剂（PAG）和光敏聚合物。 光敏聚合物与（a）至少一种具有以下各式的单体聚合：其中R 1和R 2独立地为氢原子，烷基，羟基烷基，烷氧基，羰基或酯，x和y独立地为1至 6，和（b）至少一种（甲基）丙烯酸酯单体，马来酸酐单体和降冰片烯单体。

公开(公告)号：US06613492B2

公开(公告)日：2003-09-02

申请号：US09933042

申请日：2001-08-21

Applicant: Si-hyeung Lee

Inventor： Si-hyeung Lee

IPC: G03C7038

CPC classification number: G03F7/0392

Abstract: A photosensitive polymer having a phenyl ring and a lactone group, and a resist composition, wherein the resist composition contains a photosensitive polymer including a monomer unit having at least one group selected from the groups indicated by the following formulas, and a photoacid generator (PAG).

公开(公告)号：US20110156159A1

公开(公告)日：2011-06-30

申请号：US13064138

申请日：2011-03-08

Applicant: Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

Inventor： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract translation: 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。

公开(公告)号：US20080203590A1

公开(公告)日：2008-08-28

申请号：US12111651

申请日：2008-04-29

Applicant: Chang-Jin KANG ,  Myeong-Cheol KIM ,  Man-Hyoung RYOO ,  Si-Hyeung LEE ,  Doo-Youl LEE

Inventor： Chang-Jin KANG ,  Myeong-Cheol KIM ,  Man-Hyoung RYOO ,  Si-Hyeung LEE ,  Doo-Youl LEE

IPC: H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Abstract translation: 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US20050266646A1

公开(公告)日：2005-12-01

申请号：US11080891

申请日：2005-03-16

Applicant: Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

Inventor： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

IPC: H01L21/76 ,  H01L21/00 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/02

CPC classification number: H01L27/10876 ,  H01L21/3083 ,  H01L27/0207

Abstract: There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.

Abstract translation: 提供了一种形成用于晶体管的凹槽的沟槽的方法及其布局。 根据本发明的一个方面的凹陷通道的布局被形成为使得开放区域跨越横向方向上的第一有源区域中的至少一个延伸，并且还跨越与第一活性物体平行的另一个第二有源区域 区域，并且延伸部被切割成不能在对角线方向上到达与第二有源区域平行的两个第三有源区域之间的隔离区域，并且在纵向方向上具有彼此面对的鼻子，并且布局 包括不连续对准的多个开放区域的对准。 使用布局形成蚀刻掩模，并且使用蚀刻掩模蚀刻半导体衬底，并且在有源区上形成用于凹陷沟道的沟槽。

公开(公告)号：US08193047B2

公开(公告)日：2012-06-05

申请号：US12654798

申请日：2010-01-04

Applicant: Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

Inventor： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC: H01L21/8239

CPC classification number: H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract translation: 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。

公开(公告)号：US08080886B2

公开(公告)日：2011-12-20

申请号：US12111651

申请日：2008-04-29

Applicant: Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

Inventor： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

IPC: H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Abstract translation: 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US07381508B2

公开(公告)日：2008-06-03

申请号：US10867468

申请日：2004-06-14

Applicant: Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

Inventor： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

IPC: G03F9/00 ,  G03F7/20

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Abstract translation: 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。