公开(公告)号：US20150097251A1

公开(公告)日：2015-04-09

申请号：US14569597

申请日：2014-12-12

申请人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

发明人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US08916460B1

公开(公告)日：2014-12-23

申请号：US14270315

申请日：2014-05-05

申请人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

发明人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US09190407B2

公开(公告)日：2015-11-17

申请号：US14569597

申请日：2014-12-12

申请人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

发明人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US20220351184A1

公开(公告)日：2022-11-03

申请号：US17425183

申请日：2020-01-23

申请人： Geum Cheol KIM

发明人： Geum Cheol KIM

IPC分类号： G06Q20/34 ,  G06Q20/20 ,  G06Q20/40

摘要： In online payment using the URL&CC, the routes of the payment request process and the user confirmation process are different and the order of these can be changed. (Payment method 1) Payment method 1 first requests payment by using the URL&CC's CCI path, and confirms the user by using the URL&CC's URL path and the user's URL PWD path. (Payment method 2) Payment method 2 confirms the user by using the URL&CC's URL path and the user's URL PWD path, and requests the payment by using the URL&CC's CCI path.

公开(公告)号：US20200046474A1

公开(公告)日：2020-02-13

申请号：US16340099

申请日：2017-01-10

申请人： Jong Cheol KIM ,  MEGAGEN IMPLANT CO., LTD.

发明人： Jong Cheol KIM ,  Kwang Bum PARK

IPC分类号： A61C13/34 ,  G06T7/33 ,  G06T19/20 ,  A61C9/00

摘要： An image generation system for implant diagnosis includes a first image information acquirement apparatus acquiring first three-dimensional (3D) image data about a mouth area of a target patient, a second image information acquirement apparatus acquiring second 3D image data by scanning plaster patterns of teeth of the target patient, and a data processing apparatus receiving and matching the first 3D image data and the second 3D image data and generating synthetic 3D image data. In the image generation system, the plaster patterns of teeth are provided with a matching reference marker for matching the first 3D image data and the second 3D image data, and the data processing apparatus pre-matches the first 3D image data and the second 3D image data based on a coordinate of a matching reference marker of the second 3D image data.

公开(公告)号：US10237093B2

公开(公告)日：2019-03-19

申请号：US13288762

申请日：2011-11-03

申请人： Hyun-Cheol Kim ,  Sung-Kwon Jo ,  Myung-Kwang Byun

发明人： Hyun-Cheol Kim ,  Sung-Kwon Jo ,  Myung-Kwang Byun

IPC分类号： H04B1/707 ,  H04L25/02 ,  H04B1/7107

摘要： A method and an apparatus apply an adaptive weight in a wireless communication system. In the method, channel estimation is performed. A weighting factor that reduces a Mean Square Error (MSE) is determined with respect to a channel in a specific section. A channel estimate value is multiplied by the weighting factor.

公开(公告)号：US09529705B2

公开(公告)日：2016-12-27

申请号：US14619142

申请日：2015-02-11

申请人： Hyun-Cheol Kim ,  Jinyeong Kim ,  Dae-Hoon Jang

发明人： Hyun-Cheol Kim ,  Jinyeong Kim ,  Dae-Hoon Jang

IPC分类号： G06F13/00 ,  G06F12/02 ,  G06F3/06

CPC分类号： G06F12/02 ,  G06F3/0652 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7201 ,  G06F2212/7205

摘要： A method of operating a memory controller controlling a nonvolatile memory device including a user area and a meta area is provided. The method includes selecting a source block among a plurality of memory blocks included in the user area, loading a mapping table stored in the meta area on the basis of a sub-bitmap of the selected source block, and generating a valid page layout constituted by valid pages among pages included in the source block on the basis of the loaded mapping table. The sub-bitmap includes information of a valid mapping table with respect to the selected source block.

摘要翻译： 提供了一种操作控制包括用户区域和元区域的非易失性存储器件的存储器控​​制的方法。 该方法包括：在包括在用户区域中的多个存储块之中选择源块，基于所选源块的子位图加载存储在元区中的映射表，并生成由 基于加载的映射表，源块中包含的页面之间的有效页面。 子位图包括关于所选源块的有效映射表的信息。

公开(公告)号：US20160300949A1

公开(公告)日：2016-10-13

申请号：US15062553

申请日：2016-03-07

申请人： Tae-Jong LEE ,  Sanghyuk HONG ,  TaeYong KWON ,  Sunjung KIM ,  Cheol KIM

发明人： Tae-Jong LEE ,  Sanghyuk HONG ,  TaeYong KWON ,  Sunjung KIM ,  Cheol KIM

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/08 ,  H01L29/16

摘要： Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

摘要翻译： 提供半导体器件及其制造方法。 制造半导体器件的方法可以包括提供包括从衬底突出的有源图案的衬底，在衬底上形成第一衬里层和场隔离图案以覆盖有源图案的下部，形成第二衬垫层 有源图案的上部和场隔离图案，并且在第二衬垫层上形成伪栅极。

公开(公告)号：US09409260B2

公开(公告)日：2016-08-09

申请号：US14361961

申请日：2012-06-15

申请人： Jong Jun Kim ,  Jong Cheol Kim ,  Hyeong Soon Moon

发明人： Jong Jun Kim ,  Jong Cheol Kim ,  Hyeong Soon Moon

IPC分类号： B23K1/00 ,  B23K37/02 ,  B23K37/053

CPC分类号： B23K37/0276 ,  B23K37/0217 ,  B23K37/0533 ,  B23K2101/10

摘要： Provided is a guide frame support device for a pipe welding device, the guide frame support device, which supports a guide frame provided on an outer circumferential surface of a pipe to be welded, including: a hinge bar connected to an inner circumferential surface of the guide frame; a pair of support bars which rotates around the hinge bar at a predetermined angle; hinge links, one side of each of which is hinge-connected to both ends of the hinge bar and the other side of each of which is connected to both ends of the pair of support bars; and a torsion spring provided between the pair of support bars and for providing elastic force to enable the support bars to rotate around the hinge bar at a predetermined angle.

摘要翻译： 本发明提供一种用于管道焊接装置的引导框架支撑装置，该支撑装置支撑设置在待焊接管的外周面上的引导框架，该引导框架包括：铰接杆，其连接到待焊接的管的内周面 引导框架 一对以预定角度围绕铰链杆旋转的支撑杆; 铰链连杆，其中的每一个铰链连接到铰链杆的两端，另一侧连接到该对支撑杆的两端; 以及设置在所述一对支撑杆之间并且用于提供弹性力以使所述支撑杆能够以预定角度围绕所述铰链杆旋转的扭转弹簧。

公开(公告)号：US20160218010A1

公开(公告)日：2016-07-28

申请号：US14975932

申请日：2015-12-21

申请人： Bok-Young LEE ,  Yoo-Jung LEE ,  Dong-Hoon KHANG ,  Do-Hyoung KIM ,  Cheol KIM ,  In-Hee LEE ,  Ji-Eun HAN

发明人： Bok-Young LEE ,  Yoo-Jung LEE ,  Dong-Hoon KHANG ,  Do-Hyoung KIM ,  Cheol KIM ,  In-Hee LEE ,  Ji-Eun HAN

IPC分类号： H01L21/28 ,  H01L27/11 ,  H01L29/66

CPC分类号： H01L21/28132 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/66545

摘要： A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.

摘要翻译： 一种方法包括在衬底上形成第一蚀刻目标层和第一掩模层。 在第一方向上在第一掩模层上形成沿第一方向延伸的牺牲图案。 垫片形成在牺牲图案的侧壁上。 在去除牺牲图案之后，使用间隔件作为蚀刻掩模来蚀刻第一掩模层以形成第一掩模。 第二掩模形成在每个第一掩模的侧壁上以限定包括每个第一掩模的第三掩模和在每个第一掩模的侧壁上的第二掩模。 使用第一和第三掩模蚀刻第一蚀刻目标层作为蚀刻掩模，以分别在第一和第二区域中形成第一和第二图案。 每个第一图案具有第一宽度，并且每个第二图案具有大于第一宽度的第二宽度。