公开(公告)号：US09966375B2

公开(公告)日：2018-05-08

申请号：US15049648

申请日：2016-02-22

申请人： Yong-Joon Choi ,  Tae-Yong Kwon ,  Mirco Cantoro ,  Chang-Jae Yang ,  Dong-Hoon Khang ,  Woo-Ram Kim ,  Cheol Kim ,  Seung-Jin Mun ,  Seung-Mo Ha ,  Do-Hyoung Kim ,  Seong-Ju Kim ,  So-Ra You ,  Woong-ki Hong

发明人： Yong-Joon Choi ,  Tae-Yong Kwon ,  Mirco Cantoro ,  Chang-Jae Yang ,  Dong-Hoon Khang ,  Woo-Ram Kim ,  Cheol Kim ,  Seung-Jin Mun ,  Seung-Mo Ha ,  Do-Hyoung Kim ,  Seong-Ju Kim ,  So-Ra You ,  Woong-ki Hong

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/11 ,  H01L29/165

CPC分类号： H01L27/0924 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.

公开(公告)号：US09698151B2

公开(公告)日：2017-07-04

申请号：US15179068

申请日：2016-06-10

申请人： Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

发明人： Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

IPC分类号： H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L27/11565 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54453

摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

公开(公告)号：US20170103993A1

公开(公告)日：2017-04-13

申请号：US15179068

申请日：2016-06-10

申请人： Seung-Min LEE ,  Hoo-Sung CHO ,  Jeong-Seok NAM ,  Jong-Min LEE ,  Yong-Joon CHOI

发明人： Seung-Min LEE ,  Hoo-Sung CHO ,  Jeong-Seok NAM ,  Jong-Min LEE ,  Yong-Joon CHOI

IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L27/11565 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54453

摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

公开(公告)号：US20150097251A1

公开(公告)日：2015-04-09

申请号：US14569597

申请日：2014-12-12

申请人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

发明人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US08927384B2

公开(公告)日：2015-01-06

申请号：US13400993

申请日：2012-02-21

申请人： Jong-Kyu Kim ,  Sangsup Jeong ,  Kukhan Yoon ,  Junsoo Lee ,  SungII Cho ,  Yong-Joon Choi

发明人： Jong-Kyu Kim ,  Sangsup Jeong ,  Kukhan Yoon ,  Junsoo Lee ,  SungII Cho ,  Yong-Joon Choi

IPC分类号： H01L21/20 ,  H01L27/108 ,  H01L49/02 ,  H01L27/02 ,  H01L21/311

CPC分类号： H01L28/91 ,  H01L21/31144 ,  H01L27/0203 ,  H01L27/10817 ,  H01L27/10852

摘要： A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.

摘要翻译： 一种制造半导体存储器件的方法包括：使用镶嵌方法在堆叠在衬底上的下模层上形成硬掩模图案，并使用硬掩模图案蚀刻下模层作为蚀刻掩模，以在硬掩模之下限定突起 模式。 在蚀刻的下模层的顶表面上形成支撑图案，蚀刻的下模层的顶表面位于比突起的顶表面更低的水平。 形成由支撑图案支撑的下电极。

公开(公告)号：US08704283B2

公开(公告)日：2014-04-22

申请号：US12724450

申请日：2010-03-16

申请人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Heung-Sik Park ,  Kuk-Han Yoon ,  Yong-Joon Choi

发明人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Heung-Sik Park ,  Kuk-Han Yoon ,  Yong-Joon Choi

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.

摘要翻译： 半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。 支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。 支撑构件的第一部分突出在下电极的上方。

公开(公告)号：US20110222339A1

公开(公告)日：2011-09-15

申请号：US13044683

申请日：2011-03-10

申请人： Sung-Hoon Kim ,  Jai-Hyuk Song ,  Yong-Joon Choi

发明人： Sung-Hoon Kim ,  Jai-Hyuk Song ,  Yong-Joon Choi

IPC分类号： G11C16/28 ,  G11C16/10 ,  G11C16/08

CPC分类号： G11C16/3418 ,  G11C16/10 ,  G11C16/28

摘要： Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select line; a first word line adjacent to the dummy word line; and a second word line disposed between the string select line and the first word line. The nonvolatile memory device is configured to apply a voltage to the dummy word line. When programming a memory cell connected to the first word line, a first dummy word line voltage lower than a voltage applied to the second word line is applied to the dummy word line. When programming a memory cell connected to the second word line, a second dummy word line voltage between a voltage applied to the first word line and the first dummy word line voltage is applied to the dummy word line. Accordingly, when a program operation is performed, a charge loss of a memory cell connected to a word line adjacent to a dummy word line can be reduced by changing a voltage applied to the dummy word line according to a select word line.

摘要翻译： 提供一种非易失性存储器件及其操作方法。 根据本发明构思的实施例的非易失性存储器件可以包括串选择线; 地选线; 与地面选择线相邻的虚拟字线; 与虚拟字线相邻的第一字线; 以及设置在所述串选择线和所述第一字线之间的第二字线。 非易失性存储器件被配置为向虚拟字线施加电压。 当编程连接到第一字线的存储单元时，低于施加到第二字线的电压的第一虚拟字线电压被施加到虚拟字线。 当编程连接到第二字线的存储单元时，施加到第一字线的电压和第一虚拟字线电压之间的第二虚拟字线电压被施加到伪字线。 因此，当执行编程操作时，可以通过根据选择字线改变施加到虚拟字线的电压来减少连接到与虚拟字线相邻的字线的存储单元的电荷损失。

公开(公告)号：US06806518B2

公开(公告)日：2004-10-19

申请号：US10794508

申请日：2004-03-05

申请人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

发明人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

IPC分类号： H01L2710

CPC分类号： H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.

公开(公告)号：US06743881B2

公开(公告)日：2004-06-01

申请号：US10257531

申请日：2003-04-16

申请人： Deog-Bae Kim ,  Hyeon-Jin Kim ,  Yong-Joon Choi ,  Yoon-Sik Chung

发明人： Deog-Bae Kim ,  Hyeon-Jin Kim ,  Yong-Joon Choi ,  Yoon-Sik Chung

IPC分类号： C08F21206

CPC分类号： G03F7/0392

摘要： The present invention relates to a polymer for a chemically amplified resist and a resist composition using the same. The present invention provides a polymer represented by the Formula (1) and a chemically resist composition for deep ultraviolet light comprising the same, The chemically amplified resist composition comprising the polymer represented by the formula (1) of the present invention responds process and can embody a micro-paten of high resolution on a substrate.

摘要翻译： 本发明涉及一种用于化学放大抗蚀剂的聚合物和使用其的抗蚀剂组合物。 本发明提供由式（1）表示的聚合物和包含该聚合物的用于深紫外光的化学抗蚀剂组合物。包含本发明式（1）表示的聚合物的化学增幅抗蚀剂组合物响应过程并且可以体现 在基板上具有高分辨率的微孔板。

公开(公告)号：US20170271351A1

公开(公告)日：2017-09-21

申请号：US15612229

申请日：2017-06-02

申请人： Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

发明人： Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

IPC分类号： H01L27/11565 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L21/768 ,  H01L23/544 ,  H01L27/11582 ,  H01L23/522

CPC分类号： H01L27/11565 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54453

摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.