公开(公告)号：US20060170103A1

公开(公告)日：2006-08-03

申请号：US11344550

申请日：2006-01-30

申请人： Bong-seok Suh ,  Seung-man Choi ,  Hong-Jae Shin ,  Young-jin Wee

发明人： Bong-seok Suh ,  Seung-man Choi ,  Hong-Jae Shin ,  Young-jin Wee

IPC分类号： H01L23/52

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L21/76864 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.

摘要翻译： 提供了包括可靠互连的半导体器件及其制造方法。 半导体器件包括衬底，具有开口的金属间电介质（IMD）图案，形成在开口的内表面上的非晶金属氮化物层，形成在非晶金属氮化物层上的扩散阻挡层，以及导电层 填充到具有扩散阻挡层的开口中。

公开(公告)号：US20060289999A1

公开(公告)日：2006-12-28

申请号：US11389868

申请日：2006-03-27

申请人： Hyo-Jong Lee ,  Sun-Jung Lee ,  Bong-Seok Suh ,  Hong-Jae Shin ,  Nae-In Lee ,  Kyoung-Woo Lee ,  Se-Young Jeong ,  Jeong-Hoon Ahn ,  Soo-Geun Lee

发明人： Hyo-Jong Lee ,  Sun-Jung Lee ,  Bong-Seok Suh ,  Hong-Jae Shin ,  Nae-In Lee ,  Kyoung-Woo Lee ,  Se-Young Jeong ,  Jeong-Hoon Ahn ,  Soo-Geun Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76864 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed in the dielectric. The first interconnection has a first pure copper pattern. In addition, a second interconnection having a larger width than the first interconnection is formed in the dielectric. The second interconnection has a copper alloy pattern. The copper alloy pattern may be an alloy layer formed of copper (Cu) and an additive material. A method of forming the selective copper alloy pattern is also provided.

摘要翻译： 提供半导体器件中的选择性铜合金互连。 互连包括衬底，形成在衬底上的电介质和形成在电介质中的第一互连。 第一个互连具有第一个纯铜图案。 此外，在电介质中形成具有大于第一互连的宽度的第二互连。 第二互连具有铜合金图案。 铜合金图案可以是由铜（Cu）和添加剂材料形成的合金层。 还提供了形成选择性铜合金图案的方法。

公开(公告)号：US07192864B2

公开(公告)日：2007-03-20

申请号：US11049730

申请日：2005-02-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/02063 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76835

摘要： The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

摘要翻译： 本发明公开了一种制造用于半导体器件的互连线的方法。 该方法包括在半导体衬底上形成层间绝缘层。 通过层间绝缘层形成通孔。 形成通孔填充材料以填充通孔。 在通孔填充材料上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为蚀刻掩模对通孔填充材料和层间绝缘层进行各向异性蚀刻以形成沟槽。 使用两次湿式蚀刻工艺去除通孔填充材料的剩余部分。 在去除通孔填充材料的剩余部分之后，在通孔和沟槽中形成导电层图案。

公开(公告)号：US07635645B2

公开(公告)日：2009-12-22

申请号：US11028515

申请日：2005-01-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76829

摘要： Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

摘要翻译： 公开了形成互连线和互连线结构的方法。 该方法包括在半导体衬底上形成层间绝缘层，其中层间绝缘层由碳掺杂的低k电介质层形成。 在层间绝缘层上形成氧化阻隔层。 在氧化阻挡层上形成氧化物覆盖层。 通孔位于氧化物覆盖层，氧化阻挡层和层间绝缘层中。 导电层图案形成在通孔内。

公开(公告)号：US20050176236A1

公开(公告)日：2005-08-11

申请号：US11049730

申请日：2005-02-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/3205 ,  H01L21/02 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/02063 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76835

摘要： The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

摘要翻译： 本发明公开了一种制造用于半导体器件的互连线的方法。 该方法包括在半导体衬底上形成层间绝缘层。 通过层间绝缘层形成通孔。 形成通孔填充材料以填充通孔。 在通孔填充材料上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为蚀刻掩模对通孔填充材料和层间绝缘层进行各向异性蚀刻以形成沟槽。 使用两次湿式蚀刻工艺去除通孔填充材料的剩余部分。 在去除通孔填充材料的剩余部分之后，在通孔和沟槽中形成导电层图案。

公开(公告)号：US20050161821A1

公开(公告)日：2005-07-28

申请号：US11028515

申请日：2005-01-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76829

摘要： Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

摘要翻译： 公开了形成互连线和互连线结构的方法。 该方法包括在半导体衬底上形成层间绝缘层，其中层间绝缘层由碳掺杂的低k电介质层形成。 在层间绝缘层上形成氧化阻隔层。 在氧化阻挡层上形成氧化物覆盖层。 通孔位于氧化物覆盖层，氧化阻挡层和层间绝缘层中。 导电层图案形成在通孔内。

公开(公告)号：US07417302B2

公开(公告)日：2008-08-26

申请号：US11174864

申请日：2005-07-05

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

摘要翻译： 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有台阶部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

公开(公告)号：US20060009065A1

公开(公告)日：2006-01-12

申请号：US11174864

申请日：2005-07-05

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

IPC分类号： H01R4/24

CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

摘要翻译： 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有阶梯部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

公开(公告)号：US08339349B2

公开(公告)日：2012-12-25

申请号：US12318272

申请日：2008-12-23

申请人： Hong-Jae Shin ,  Jeom-Jae Kim ,  Mike (J. S.) Lee

发明人： Hong-Jae Shin ,  Jeom-Jae Kim ,  Mike (J. S.) Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2320/0223 ,  G09G2330/08

摘要： A gate driving unit for a liquid crystal display device including a plurality of liquid crystal pixels, first to Nth gate lines, a plurality of liquid crystal capacitors and a plurality of thin film transistors, includes first and second clock signal lines for providing first and second clock signals; first to Nth shift registers respectively corresponding to the first to Nth gate lines, the first to Nth shift registers receiving one of the first clock signal and the second clock signal and outputting first to Nth scanning signals, respectively; a redundant repair shift register as (N+1)th shift register receiving one of first and second clock signals and outputting a repair scanning signal; a plurality of first switches for respectively connecting one of the first and second clock signal lines to the first to Nth shift registers and the redundant repair shift register; a plurality of second switches for respectively switching a connection of the first to Nth shift registers with the first to Nth gate lines; and a plurality of third switches for respectively switching a connection of the second to Nth shift registers and the redundant repair shift register with the first to Nth gate lines, wherein N is positive integer.

摘要翻译： 一种用于液晶显示装置的栅极驱动单元，包括多个液晶像素，第一至第N栅极线，多个液晶电容器和多个薄膜晶体管，包括第一和第二时钟信号线，用于提供第一和第二 时钟信号; 分别对应于第一至第N栅极线的第一至第N移位寄存器，第一至第N移位寄存器分别接收第一时钟信号和第二时钟信号之一并分别输出第一至第N扫描信号; 作为第（N + 1）移位寄存器的冗余修复移位寄存器，接收第一和第二时钟信号之一并输出修复扫描信号; 多个第一开关，用于分别将第一和第二时钟信号线中的一个连接到第一至第N移位寄存器和冗余修复移位寄存器; 多个第二开关，用于分别切换第一至第N移位寄存器与第一至第N栅极线的连接; 以及多个第三开关，用于分别用第一至第N栅极线切换第二至第N移位寄存器和冗余修复移位寄存器的连接，其中N为正整数。

公开(公告)号：US07989335B2

公开(公告)日：2011-08-02

申请号：US12661885

申请日：2010-03-25

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin

IPC分类号： H01L21/44

CPC分类号： H01L27/10852 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L28/91

摘要： In a method of forming an insulation layer pattern, an insulation layer is formed on a substrate. An organic layer and a hard mask layer are successively formed on the insulation layer. A preliminary hard mask pattern having first openings is formed by patterning the hard mask layer. A hard mask pattern having the first openings and second openings is formed by patterning the preliminary hard mask pattern. Width control spacers are formed on sidewalls of the first and the second openings. An etching mask pattern is formed by etching the organic layer using the hard mask pattern as an etching mask. The insulation layer pattern having third openings is formed by etching the insulation layer using the etching mask pattern as an etching mask.

摘要翻译： 在形成绝缘层图案的方法中，在基板上形成绝缘层。 在绝缘层上依次形成有机层和硬掩模层。 通过图案化硬掩模层形成具有第一开口的初步硬掩模图案。 具有第一开口和第二开口的硬掩模图案通过图案化初步硬掩模图案而形成。 宽度控制间隔件形成在第一和第二开口的侧壁上。 通过使用硬掩模图案作为蚀刻掩模蚀刻有机层来形成蚀刻掩模图案。 通过使用蚀刻掩模图案作为蚀刻掩模蚀刻绝缘层来形成具有第三开口的绝缘层图案。