公开(公告)号：US08228069B2

公开(公告)日：2012-07-24

申请号：US12344024

申请日：2008-12-24

申请人： Sun-Jung Lee ,  Hong-Jae Shin

发明人： Sun-Jung Lee ,  Hong-Jae Shin

IPC分类号： G01R31/08

CPC分类号： G01R31/31717 ,  G11C11/41 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008

摘要： A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.

摘要翻译： 测试装置包括在半导体衬底上的多对测试触点; 第一测试结构，其包括多个第一测试互连层和电连接到第一测试互连层的第一体互连层，每个第一测试互连层电连接到至少一个测试接触; 以及第二测试结构，其包括多个第二测试互连层和电连接到第二测试互连层的第二体互连层，每个第二测试互连层电连接到至少一个测试接触。

公开(公告)号：US07928002B2

公开(公告)日：2011-04-19

申请号：US12396632

申请日：2009-03-03

申请人： Mu-kyeng Jung ,  Sun-jung Lee ,  Ki-chul Park

发明人： Mu-kyeng Jung ,  Sun-jung Lee ,  Ki-chul Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.

摘要翻译： 一种形成半导体器件的布线层的方法，包括形成第一层间绝缘层，以具有对应于待形成在支撑层上的层间绝缘层的厚度的一部分的第一厚度并形成第一接触 插入第一层间绝缘层。 该方法还包括在第一接触插塞和第一层间绝缘层上形成具有第二厚度的第二层间绝缘层，从而形成层间绝缘层，其中第二厚度对应于层间绝缘层的其余厚度 并且形成与所述第二层间绝缘层中的所述第一接触插塞连接的第二接触插塞，由此形成包括所述第一接触插塞和所述第二接触插塞的局部布线层。

公开(公告)号：US07655525B2

公开(公告)日：2010-02-02

申请号：US11848991

申请日：2007-08-31

申请人： Sun-jung Lee ,  Hong-jae Shin ,  Bong-seok Suh

发明人： Sun-jung Lee ,  Hong-jae Shin ,  Bong-seok Suh

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/4763

CPC分类号： H01L29/66515 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.

摘要翻译： 根据本发明的示例性实施例的防止栅极间隔物应力和硅化物区域的物理和化学损伤的半导体器件及其制造方法包括：衬底，形成在衬底中的隔离区域，栅极图案 形成在衬底上的隔离区域之间，与栅极图案的侧壁相邻并延伸到衬底表面的L型衬垫，形成在衬底上的L型间隔物延伸的端部之间的源极/漏极硅化物区域 通过与源极/漏极硅化物区域电连接的插塞到衬底的表面和隔离区域，与L型间隔物相邻并填充形成在栅极上的通孔塞层之间的空间的层间电介质层 图案和衬底，以及形成在层间电介质层上的信号传输线。

公开(公告)号：US20090227101A1

公开(公告)日：2009-09-10

申请号：US12396632

申请日：2009-03-03

申请人： Mu-kyeng JUNG ,  Sun-jung LEE ,  Ki-chul PARK

发明人： Mu-kyeng JUNG ,  Sun-jung LEE ,  Ki-chul PARK

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76895 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.

摘要翻译： 一种形成半导体器件的布线层的方法，包括形成第一层间绝缘层，以具有对应于待形成在支撑层上的层间绝缘层的厚度的一部分的第一厚度并形成第一接触 插入第一层间绝缘层。 该方法还包括在第一接触插塞和第一层间绝缘层上形成具有第二厚度的第二层间绝缘层，从而形成层间绝缘层，其中第二厚度对应于层间绝缘层的其余厚度 并且形成与所述第二层间绝缘层中的所述第一接触插塞连接的第二接触插塞，由此形成包括所述第一接触插塞和所述第二接触插塞的局部布线层。

公开(公告)号：US20090167319A1

公开(公告)日：2009-07-02

申请号：US12344024

申请日：2008-12-24

申请人： Sun-Jung Lee ,  Hong-Jae Shin

发明人： Sun-Jung Lee ,  Hong-Jae Shin

IPC分类号： G01R31/28

CPC分类号： G01R31/31717 ,  G11C11/41 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008

摘要： A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.

摘要翻译： 测试装置包括在半导体衬底上的多对测试触点; 第一测试结构，其包括多个第一测试互连层和电连接到第一测试互连层的第一体互连层，每个第一测试互连层电连接到至少一个测试接触; 以及第二测试结构，其包括多个第二测试互连层和电连接到第二测试互连层的第二体互连层，每个第二测试互连层电连接到至少一个测试接触。

公开(公告)号：US20070298600A1

公开(公告)日：2007-12-27

申请号：US11425841

申请日：2006-06-22

申请人： Bong-seok Suh ,  Hong-jae Shin ,  Sun-jung Lee ,  Min-chul Sun ,  Jung-hoon Lee

发明人： Bong-seok Suh ,  Hong-jae Shin ,  Sun-jung Lee ,  Min-chul Sun ,  Jung-hoon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/76846

摘要： A method of fabricating a semiconductor device and a semiconductor device fabricated thereby. The method of fabricating the semiconductor device includes forming gate electrodes on a semiconductor substrate; forming source/drain regions within the semiconductor substrate so as to be located at both sides of each of the gate electrodes; forming a nickel silicide layer on surfaces of the gate electrodes and the source/drain regions by evaporating nickel or nickel alloy on the semiconductor substrate formed with the gate electrodes and the source/drain regions and then performing a thermal process on the nickel or the nickel alloy; forming an interlayer insulating layer, which is formed with contact holes through which a surface of the nickel silicide layer is exposed, on a surface obtained after the above processes have been performed; forming an ohmic layer by evaporating a refractory metal conformably along the contact holes, the refractory metal being converted to silicide at a temperature of 500° C. or more; forming a diffusion barrier on the ohmic layer conformably along the contact holes; and forming a metal layer by burying a metal material within the contact holes.

摘要翻译： 一种制造半导体器件的方法及其制造的半导体器件。 制造半导体器件的方法包括在半导体衬底上形成栅电极; 在半导体衬底内形成源/漏区，以便位于每个栅电极的两侧; 通过在形成有栅电极和源极/漏极区域的半导体衬底上蒸发镍或镍合金，然后在镍或镍上进行热处理，在栅电极和源/漏区的表面上形成硅化镍层 合金; 形成层间绝缘层，所述层间绝缘层在进行上述处理后得到的表面上形成有暴露所述镍硅化物层的表面的接触孔; 通过沿着接触孔顺应蒸发难熔金属形成欧姆层，难熔金属在500℃或更高的温度下转化为硅化物; 在欧姆层上沿着接触孔顺应地形成扩散阻挡层; 以及通过在接触孔内埋入金属材料来形成金属层。

公开(公告)号：US20050087893A1

公开(公告)日：2005-04-28

申请号：US10997902

申请日：2004-11-29

申请人： Seung-pil Chung ,  Kyu-whan Chang ,  Sun-jung Lee ,  Kun-tack Lee ,  Im-soo Park ,  Kwang-wook Lee ,  Moon-hee Lee

发明人： Seung-pil Chung ,  Kyu-whan Chang ,  Sun-jung Lee ,  Kun-tack Lee ,  Im-soo Park ,  Kwang-wook Lee ,  Moon-hee Lee

IPC分类号： H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/02057 ,  H01L21/31116

摘要： A method for removing an oxide layer such as a natural oxide layer and a semiconductor manufacturing apparatus which uses the method to remove the oxide layer. A vertically movable susceptor is installed at the lower portion in a processing chamber and a silicon wafer is loaded onto the susceptor when it is at the lower portion of the processing chamber. The air is exhausted from the processing chamber to form a vacuum condition therein. A hydrogen gas in a plasma state and a fluorine-containing gas are supplied into the processing chamber to induce a chemical reaction with the oxide layer on the silicon wafer, resulting in a reaction layer. Then, the susceptor is moved up to the upper portion of the processing chamber, to anneal the silicon wafer on the susceptor with a heater installed at the upper portion of the processing chamber, thus vaporizing the reaction layer. The vaporized reaction layer is exhausted out of the chamber. The oxide layer can be removed with a high selectivity while avoiding damage or contamination of the underlying layer.

摘要翻译： 用于除去氧化物层的方法，例如天然氧化物层和使用该方法去除氧化物层的半导体制造装置。 垂直移动的基座安装在处理室的下部处，并且当硅晶片位于处理室的下部时，将硅晶片装载到基座上。 空气从处理室排出，在其中形成真空条件。 将等离子体状态的氢气和含氟气体供给到处理室，以引起与硅晶片上的氧化物层的化学反应，产生反应层。 然后，将基座向上移动到处理室的上部，通过安装在处理室上部的加热器对基座上的硅晶片退火，从而使反应层蒸发。 蒸发的反应层被排出室外。 可以以高选择性去除氧化物层，同时避免下层的损坏或污染。

公开(公告)号：US07541276B2

公开(公告)日：2009-06-02

申请号：US11223311

申请日：2005-09-09

申请人： Jae Hak Kim ,  Sun Jung Lee ,  Seung Jin Lee

发明人： Jae Hak Kim ,  Sun Jung Lee ,  Seung Jin Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/7685

摘要： Exemplary embodiments of the invention generally include methods for forming multilayer metal interconnect structures using dual damascene methods that incorporate a via capping process to protect lower interconnection lines from etching damage or oxidation, for example, that may be caused by inadvertent exposure of lower interconnection lines to etching atmospheres.

摘要翻译： 本发明的示例性实施例通常包括使用双镶嵌方法形成多层金属互连结构的方法，该方法包括通孔封盖工艺以保护较低的互连线免受蚀刻损伤或氧化，例如可能由于下层互连线的无意曝光而引起 蚀刻气氛。

公开(公告)号：US20060154465A1

公开(公告)日：2006-07-13

申请号：US11330581

申请日：2006-01-12

申请人： Bong-seok Suh ,  Sun-jung Lee ,  Hong-jae Shin ,  Soo-geun Lee

发明人： Bong-seok Suh ,  Sun-jung Lee ,  Hong-jae Shin ,  Soo-geun Lee

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a method for fabricating an interconnection line in a semiconductor device. The method includes forming a dielectric layer pattern including a region for forming the interconnection line on a semiconductor substrate, forming a diffusion barrier layer on the dielectric layer pattern, forming a first adhesion layer on the diffusion barrier layer, forming a seed layer on the first adhesion layer, forming a conductive layer to fill the region for forming the interconnection line, performing grain growth of the conductive layer by performing a first annealing process, planarizing the conductive layer to expose the top surface of the dielectric layer pattern, and forming an interface layer through reaction between the first adhesion layer and the conductive layer by performing a second annealing process at a temperature higher than that of the first annealing process.

摘要翻译： 提供一种在半导体器件中制造互连线的方法。 该方法包括在半导体衬底上形成包括用于形成互连线的区域的电介质层图案，在电介质层图案上形成扩散阻挡层，在扩散阻挡层上形成第一粘附层，在第一层上形成晶种层 形成导电层以填充用于形成互连线的区域，通过执行第一退火工艺来执行导电层的晶粒生长，使导电层平坦化以暴露电介质层图案的顶表面，以及形成界面 通过在高于第一退火处理的温度下进行第二退火处理，在第一粘附层和导电层之间反应层。

公开(公告)号：US06485712B1

公开(公告)日：2002-11-26

申请号：US10035233

申请日：2002-01-04

申请人： Won Kyu Kim ,  Kye Won Lee ,  Sun Jung Lee ,  Bong Jun Kim ,  Hye Young Lee ,  Chul Hong Park ,  Dong Soo Kim ,  Kyeong Bum Choi ,  Eun Joung Yoo

发明人： Won Kyu Kim ,  Kye Won Lee ,  Sun Jung Lee ,  Bong Jun Kim ,  Hye Young Lee ,  Chul Hong Park ,  Dong Soo Kim ,  Kyeong Bum Choi ,  Eun Joung Yoo

IPC分类号： A61K742

CPC分类号： A61K8/37 ,  A61K8/35 ,  A61K8/9706 ,  A61Q17/04 ,  A61Q19/06

摘要： Disclosed is a UV blocking and slimming cosmetic composition containing laminaria water extract, octylmethoxycinnamate and oxybenzone.

摘要翻译： 本发明公开了一种含有叶酸水提取物，辛基甲氧基肉桂酸酯和羟基苯酮的UV阻隔和减肥化妆品组合物。