公开(公告)号：US07129719B2

公开(公告)日：2006-10-31

申请号：US10858166

申请日：2004-06-01

申请人： Boo-Yang Jung ,  Seong-Young Han ,  Bruce Kim

发明人： Boo-Yang Jung ,  Seong-Young Han ,  Bruce Kim

IPC分类号： G01R27/08 ,  G01R27/32

CPC分类号： G01R31/2853 ,  G01R31/2896

摘要： Provided is an apparatus for detecting a defect of a circuit pattern which includes a resonator, a first power supply unit connected to one end of the resonator to apply power to the resonator, a probe connected to the other end of the resonator to contact one end of the circuit pattern, a second power supply unit connected to the other end of the circuit pattern to apply a voltage thereto, and a detection portion connected between the resonator and the probe to measure a voltage generated from the circuit pattern and generate a measurement voltage, and determine presence of a defect in the circuit pattern from the measurement voltage.

摘要翻译： 提供了一种用于检测电路图案的缺陷的装置，其包括谐振器，连接到谐振器的一端以向谐振器施加功率的第一电源单元，连接到谐振器的另一端以接触一端的探针 连接到电路图案的另一端以向其施加电压的第二电源单元和连接在谐振器和探头之间的检测部分，以测量从电路图案产生的电压并产生测量电压 并且从测量电压确定电路图案中的缺陷的存在。

公开(公告)号：US20050264306A1

公开(公告)日：2005-12-01

申请号：US10858166

申请日：2004-06-01

申请人： Boo-Yang Jung ,  Seong-Young Han ,  Bruce Kim

发明人： Boo-Yang Jung ,  Seong-Young Han ,  Bruce Kim

IPC分类号： G01R31/02 ,  G01R27/08 ,  G01R31/28 ,  H02P1/46

CPC分类号： G01R31/2853 ,  G01R31/2896

摘要： Provided is an apparatus for detecting a defect of a circuit pattern which includes a resonator, a first power supply unit connected to one end of the resonator to apply power to the resonator, a probe connected to the other end of the resonator to contact one end of the circuit pattern, a second power supply unit connected to the other end of the circuit pattern to apply a voltage thereto, and a detection portion connected between the resonator and the probe to measure a voltage generated from the circuit pattern and generate a measurement voltage, and determine presence of a defect in the circuit pattern from the measurement voltage.

摘要翻译： 提供了一种用于检测电路图案的缺陷的装置，其包括谐振器，连接到谐振器的一端以向谐振器施加功率的第一电源单元，连接到谐振器的另一端以接触一端的探针 连接到电路图案的另一端以向其施加电压的第二电源单元和连接在谐振器和探头之间的检测部分，以测量从电路图案产生的电压并产生测量电压 并且从测量电压确定电路图案中的缺陷的存在。

公开(公告)号：US6111414A

公开(公告)日：2000-08-29

申请号：US126909

申请日：1998-07-31

申请人： Abijit Chatterjee ,  Bruce Kim ,  Madhavan Swaminathan

发明人： Abijit Chatterjee ,  Bruce Kim ,  Madhavan Swaminathan

IPC分类号： G01R31/04 ,  G01R31/28 ,  G01B7/14

CPC分类号： G01R31/2853 ,  G01R31/046

摘要： A system for testing interconnects in multi-chip modules including a radio frequency resonator having a resonant circuit with a relatively high quality factor, the output of the resonant circuit being attached to a probe. Electrically coupled to the resonant circuit output is an apparatus to analyze the voltage signal output. The probe is applied to one end of an interconnect. When the probe is applied, the resonant frequency of the resonant circuit and the magnitude of the frequency response are altered due to the additional loading created by the interconnect. Due to the relatively high quality factor of the resonant circuit, the magnitude of the frequency response of the altered resonant circuit is measurably distinct from a predetermined reference magnitude at a predetermined reference frequency, thus indicating the existence of a defect. Additionally, the type of defect that exists is ascertainable by determining whether the resonant frequency of the altered resonant circuit is greater or less than the reference frequency by examining, for example, the phase response.

摘要翻译： 一种用于测试多芯片模块中的互连的系统，包括具有相对较高品质因数的谐振电路的射频谐振器，谐振电路的输出连接到探头。 电耦合到谐振电路输出是分析电压信号输出的装置。 探头应用于互连的一端。 当应用探头时，谐振电路的谐振频率和频率响应的幅度由于互连产生的附加负载而改变。 由于谐振电路的质量因素相对较高，所以改变的谐振电路的频率响应的大小在预定的参考频率处与预定的参考幅度可测地不同，从而表明存在缺陷。 此外，通过检查例如相位响应来确定改变的谐振电路的谐振频率是大于还是小于参考频率，可以确定存在的缺陷的类型。

公开(公告)号：US07062004B1

公开(公告)日：2006-06-13

申请号：US09905511

申请日：2001-07-13

申请人： Gyudong Kim ,  Min-Kyu Kim ,  Ook Kim ,  Eric A. Lee ,  Bruce Kim

发明人： Gyudong Kim ,  Min-Kyu Kim ,  Ook Kim ,  Eric A. Lee ,  Bruce Kim

IPC分类号： H04L7/00

CPC分类号： H03L7/093 ,  H03L7/0898 ,  H04L7/0337

摘要： A scheme for reducing jitter in high-speed digital communication by adaptively controlling the loop bandwidth of a receiver PLL to reduce the relative jitter between the recovered data and clock. The scheme uses phase pointer activity to represent the relative jitter. The phase pointer activity is measured and used to control the receiver PLL loop bandwidth. The receiver PLL loop bandwidth is repeatedly incremented or decremented by a step size based on the comparison between a newly measured activity value and the old activity value, until the phase pointer activity reaches a minimum. Because the PLL performance requirement of the transmitter can be relaxed, compatibility with legacy transmitters and multi-vendor transmitters is enhanced. Because tight control of fabrication process parameters of PLLs may be relaxed, the fabrication yield may also be improved.

摘要翻译： 通过自适应地控制接收机PLL的环路带宽以减少恢复的数据和时钟之间的相对抖动来减少高速数字通信中的抖动的方案。 该方案使用相位指针活动来表示相对抖动。 测量相位指针活动并用于控制接收机PLL环路带宽。 基于新测量的活动值和旧活动值之间的比较，接收机PLL环路带宽被重复地增加或减小步长，直到相位指针活动达到最小值。 因为发射机的PLL性能要求可以放宽，与传统发射机和多厂商发射机的兼容性得到增强。 由于PLL的制造工艺参数的紧密控制可以被放宽，所以也可以提高制造成品率。

公开(公告)号：US06870930B1

公开(公告)日：2005-03-22

申请号：US09579811

申请日：2000-05-26

申请人： Gyudong Kim ,  Victor M. Da Costa ,  Bruce Kim ,  David D. Lee ,  Russel A. Martin ,  Seung Ho Hwang

发明人： Gyudong Kim ,  Victor M. Da Costa ,  Bruce Kim ,  David D. Lee ,  Russel A. Martin ,  Seung Ho Hwang

IPC分类号： H04L9/08 ,  H04L9/12 ,  H04L9/18 ,  H04N7/167 ,  H04N7/173 ,  H04L9/00 ,  H04K1/06

CPC分类号： G09G5/006 ,  H04L9/065 ,  H04L9/0844 ,  H04L9/12 ,  H04L2209/046 ,  H04L2209/34 ,  H04L2209/605 ,  H04N7/1675 ,  H04N7/17318 ,  H04N21/23476 ,  H04N21/44055 ,  H04N21/63345

摘要： The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a first sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+1 bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link. Subsequent to step (e) and prior to step (f), the method can further include the step of encrypting the encoded n+2 bit control characters, such that the generating step generates a serial data stream in response to the encrypted data characters and the encrypted control characters.

摘要翻译： 本发明涉及用于在传输期间保护数字内容的系统和方法。 本发明的一个方案提供了一种用于在高速数字视频传输系统中进行加密的方法，该方法包括以下步骤：a）对n位数据字的第一序列进行转换控制编码，以编码到编码的n + 1位数据字符中，其中 n是正整数，b）用XOR掩码执行编码的n + 1位数据字符的异或掩蔽，以产生掩蔽的n + 1位数据字符; c）直流平衡屏蔽的n + 1位数据字符，以产生直流平衡，屏蔽的n + 2位数据字符; d）使用扰频公式对DC平衡掩蔽的n + 2位数据字符进行加扰，以产生加密的n + 2位数据字符; e）将控制数据编码为编码的n + 2位控制字符，f）响应于加密的数据字符和编码的控制字符产生串行数据流，以及g）通过通信链路发送串行数据流。 在步骤（e）之后和步骤（f）之后，该方法还可以包括对编码的n + 2位控制字符进行加密的步骤，使得生成步骤响应于加密的数据字符生成串行数据流，并且 加密的控制字符。

公开(公告)号：US20090105983A1

公开(公告)日：2009-04-23

申请号：US12255534

申请日：2008-10-21

申请人： Pramod Variyam ,  Sudhir Wokhlu ,  Srividya Sundar ,  Venkat Kalyanaraman ,  Bruce Kim ,  Raul I. Rousselin ,  Toby O. Byrd ,  Erika L. Beskar

发明人： Pramod Variyam ,  Sudhir Wokhlu ,  Srividya Sundar ,  Venkat Kalyanaraman ,  Bruce Kim ,  Raul I. Rousselin ,  Toby O. Byrd ,  Erika L. Beskar

IPC分类号： G01R31/28

CPC分类号： G01R31/319 ,  G01R31/31905

摘要： A test definer, a method for automatically determining functional tests for a printed circuit board (PCB) having analog components and a test system. In one embodiment, the test definer includes: (1) a circuit builder configured to generate a representative circuit of the PCB based on schematic information thereof, (2) a circuit organizer configured to partition the representative circuit into testable sub-circuits and (3) a specification generator configured to automatically determine functionality tests for the PCB based on the sub-circuits, obtain expected values from the functionality tests and generate platform-independent specifications representing the functionality tests and the expected values.

摘要翻译： 测试定义器，用于自动确定具有模拟组件的印刷电路板（PCB）和测试系统的功能测试的方法。 在一个实施例中，测试定义器包括：（1）电路构造器，其被配置为基于其原理图信息生成PCB的代表性电路，（2）电路组织器，被配置为将代表性电路划分成可测试的子电路和（3 ）一个规范生成器，被配置为基于子电路自动确定PCB的功能测试，从功能测试中获得预期值，并生成表示功能测试和期望值的与平台无关的规范。

公开(公告)号：US07991096B1

公开(公告)日：2011-08-02

申请号：US10842231

申请日：2004-05-10

申请人： Bruce Kim ,  Hoon Choi ,  Gyudong Kim

发明人： Bruce Kim ,  Hoon Choi ,  Gyudong Kim

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H04J3/0608

摘要： A data sampling circuit that employs an oversampling clock to oversample a data signal, a phase tracking circuit for use in such a sampling circuit, and a receiver and system including such a sampling circuit. Preferably, phase tracking is implemented by systematically identifying and rejecting at least one worst sampling position, and sampling the data signal at a non-rejected sampling position. Preferably, phase tracking is accomplished by counting through-transitions of edges of the sampled data signal through each oversampling position, and rejecting an oversampling position having a highest count of through-transitions. In some embodiments, different phase tracking methods (at least one of which includes the step of generating through-transition counts) are used for different types of input data. Other aspects of the invention are methods for determining an oversampling position for oversampling a data signal, and methods for oversampling a data signal including by generating through-transition counts.

摘要翻译： 使用过采样时钟对数据信号进行过采样的数据采样电路，用于这种采样电路的相位跟踪电路以及包括这种采样电路的接收机和系统。 优选地，相位跟踪通过系统地识别和拒绝至少一个最差采样位置并且在未拒绝的采样位置对数据信号进行采样来实现。 优选地，通过对采样数据信号的边缘通过每个过采样位置的过渡进行计数，以及拒绝具有最高通过过渡计数的过采样位置来实现相位跟踪。 在一些实施例中，不同类型的输入数据使用不同的相位跟踪方法（其中至少一个包括生成通过转换计数的步骤）。 本发明的其它方面是用于确定用于过采样数据信号的过采样位置的方法，以及用于过采样数据信号的方法，包括通过产生通过转换计数。

公开(公告)号：US07236553B1

公开(公告)日：2007-06-26

申请号：US10763905

申请日：2004-01-23

申请人： Hoon Choi ,  Gyudong Kim ,  Daeyun Shim ,  Bruce Kim ,  Seung Ho Hwang

发明人： Hoon Choi ,  Gyudong Kim ,  Daeyun Shim ,  Bruce Kim ,  Seung Ho Hwang

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H04L7/0008

摘要： A data sampling method and circuit employing an oversampling clock to oversample a data signal, a phase tracker for use with or in a data sampling circuit, and a method for identifying a sequence of best sampling positions for sampling a data signal from signal samples generated using an oversampling clock. In some embodiments, data indicative of the phase of at least one of the oversampling clock's sampling positions relative to the center of the data eye are low-pass filtered in a manner determined by the data signal's bit rate. In other embodiments, the number of dead cycles of the phase tracker decision loop is reduced by generating possible solutions in parallel and moving the feedback point so as to occur as late as practical, or the phase tracker ignores a sample set when updating its determination of the best sampling position when the sample set indicates that the data signal has less than a predetermined number of transitions during a corresponding tracking period.

摘要翻译： 使用过采样时钟对数据信号进行过采样的数据采样方法和电路，与数据采样电路一起使用或在数据采样电路中使用的相位跟踪器，以及用于识别最佳采样位置序列的方法，用于从使用 过采样时钟。 在一些实施例中，指示相对于数据眼睛的中心的过采样时钟的采样位置中的至少一个的相位的数据以由数据信号的比特率确定的方式进行低通滤波。 在其他实施例中，相位跟踪器判定循环的死循环的数量通过并行产生可能的解并且将反馈点移动以便尽可能晚地发生而减少，或者当更新其样本集的确定时，相位跟踪器忽略样本集 当样本集合表示在对应的跟踪周期期间数据信号具有小于预定数量的转换时的最佳采样位置。

公开(公告)号：US20050021116A1

公开(公告)日：2005-01-27

申请号：US10623821

申请日：2003-07-21

申请人： Jiping He ,  Kee-Keun Lee ,  Bruce Kim ,  Amarjit Singh

发明人： Jiping He ,  Kee-Keun Lee ,  Bruce Kim ,  Amarjit Singh

IPC分类号： A61N1/05

CPC分类号： A61N1/0529

摘要： An electrode (30) implants into live tissue. The electrode has a first layer with a first silicon portion (50) forming a tip of the electrode and a second benzocyclobutene (BCB) portion (52) disposed adjacent to the first portion. A second BCB layer (56) is disposed over the first layer. A third BCB layer (58) is disposed over the second layer. The first layer further includes a third silicon portion (54) disposed adjacent to the second portion. A head-stage (40) has a connector (38) coupled for receiving the electrical signals from the electrode. A flexible substrate (90) has conductors for transmitting the electrical signals. A stiffener (94) supports a portion of the flexible substrate. An electronic circuit (96) is disposed on the flexible substrate above the stiffener and receives the electrical signals. A connector (12) is supported by the stiffener and coupled to an output of the electronic circuit.

摘要翻译： 电极（30）植入活组织。 电极具有第一层，其具有形成电极尖端的第一硅部分（50）和邻近第一部分设置的第二苯并环丁烯（BCB）部分（52B）。 第二BCB层（56）设置在第一层上。 第三BCB层（58）设置在第二层上。 第一层还包括邻近第二部分设置的第三硅部分（54）。 头级（40）具有连接器（38），其连接用于接收来自电极的电信号。 柔性基板（90）具有用于传输电信号的导体。 加强件（94）支撑柔性基板的一部分。 电子电路（96）设置在加强件上方的柔性基板上并接收电信号。 连接器（12）由加强件支撑并耦合到电子电路的输出端。

公开(公告)号：US20120306096A1

公开(公告)日：2012-12-06

申请号：US13483270

申请日：2012-05-30

申请人： Bruce Kim ,  Anurag Gupta ,  Sukeshwar Kannan ,  Falah Mohammed ,  Byoungchul Ahn

发明人： Bruce Kim ,  Anurag Gupta ,  Sukeshwar Kannan ,  Falah Mohammed ,  Byoungchul Ahn

IPC分类号： H01L23/48 ,  B82Y99/00

CPC分类号： B82Y10/00 ,  B82Y30/00 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/53276 ,  H01L29/413 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： A carbon nanotube (CNT) through silicon via (TSV) for three-dimensional (3D) substrate interconnects is described. TSV technologies provide for high performance and high density 3D packages. The CNT-based TSVs provide for integration of analog, RF and mixed-signal integrated circuits. CNT-based TSV provides superior electrical characteristics as compared to conventional TVs filled with conductive metals.

摘要翻译： 描述了用于三维（3D）衬底互连的通过硅通孔（TSV）的碳纳米管（CNT）。 TSV技术提供高性能和高密度3D封装。 基于CNT的TSV提供模拟，RF和混合信号集成电路的集成。 与传统的充满导电金属的电视相比，基于CNT的TSV提供优异的电气特性。