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    PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTODE
    3.
    发明申请
    PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTODE 有权
    具有双功能门电极的像素传感器单元

    公开(公告)号：US20120211854A1

    公开(公告)日：2012-08-23

    申请号：US13029670

    申请日：2011-02-17

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    IPC分类号： H01L31/0352 ,  G06F17/50 ,  H01L31/18

    CPC分类号： H01L27/14614

    摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

    摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。 栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。 栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。 栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。

    FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE
    6.
    发明申请
    FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 有权
    具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法

    公开(公告)号：US20090101978A1

    公开(公告)日：2009-04-23

    申请号：US11873521

    申请日：2007-10-17

    申请人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

    摘要翻译： 这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料 （例如，金属硅化物）。 以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。 以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

    Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
    7.
    发明授权
    Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure 有权
    具有合并源极/漏极硅化物的鳍型场效应晶体管结构和形成结构的方法

    公开(公告)号：US07851865B2

    公开(公告)日：2010-12-14

    申请号：US11873521

    申请日：2007-10-17

    申请人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

    摘要翻译： 这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料 （例如，金属硅化物）。 以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。 以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

    FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE
    8.
    发明申请
    FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 有权
    具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法

    公开(公告)号：US20090020819A1

    公开(公告)日：2009-01-22

    申请号：US11778217

    申请日：2007-07-16

    申请人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

    摘要： Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

    摘要翻译： 这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的实施例，其中多个散热片部分或完全由高导电材料（例如， 金属硅化物）。 以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。 以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

    CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD
    10.
    发明申请
    CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD 审中-公开
    用于修改半导体器件中的应力的接触棒及相关方法

    公开(公告)号：US20130240997A1

    公开(公告)日：2013-09-19

    申请号：US13424319

    申请日：2012-03-19

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/7843

    摘要： Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.

    摘要翻译： 公开了用于形成应力优化接触棒和触点的解决方案。 一方面，公开了一种具有源极/漏极区域的n型场效应晶体管（NFET）的半导体器件; 具有源极/漏极区域的p型场效应晶体管（PFET） 在NFET和PFET两者上的应力诱导层，应力诱导层仅引起压缩应力和拉伸应力之一; 接触棒延伸穿过应力感应层并且耦合到PFET和NFET的所选器件的源/漏区中的至少一个，以修改与在另一器件中感应的应力相比在所选器件中感应的应力; 以及延伸穿过应力感应层并且耦合到PFET和NFET的另一个器件的源极/漏极区域中的至少一个的圆形接触。