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公开(公告)号：US08637871B2
公开(公告)日：2014-01-28
申请号：US12939462
申请日：2010-11-04
IPC分类号： H01L29/15
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66659
摘要： An asymmetric hetero-structure FET and method of manufacture is provided. The structure includes a semiconductor substrate and an epitaxially grown semiconductor layer on the semiconductor substrate. The epitaxially grown semiconductor layer includes an alloy having a band structure and thickness that confines inversion carriers in a channel region, and a thicker portion extending deeper into the semiconductor structure at a doped edge to avoid confinement of the inversion carriers at the doped edge.
摘要翻译： 提供了非对称异质结构FET及其制造方法。 该结构包括在半导体衬底上的半导体衬底和外延生长的半导体层。 外延生长的半导体层包括具有限制沟道区域中的反转载流子的带结构和厚度的合金，以及在掺杂边缘处更深地延伸到半导体结构中的较厚部分，以避免在掺杂边缘处限制反转载流子。
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公开(公告)号：US20120105095A1
公开(公告)日：2012-05-03
申请号：US12938440
申请日：2010-11-03
IPC分类号： G01R31/26
CPC分类号： H01L22/32 , G01R31/2621 , G01R31/2644 , G01R31/2884 , H01L22/34 , H01L27/1203 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： A circuit for testing a floating body field-effect transistor (FET), and a related method, are provided. Embodiments of this invention include a circuit including a contacted-body FET structure that can be operated in a floating body mode or a body-contacted mode, and a passgate FET. A body of the contacted-body FET structure is connected to the drain of the passgate FET. Voltage can be applied to the passgate FET to either allow or restrict current flow through the passgate FET, to operate the contacted-body FET structure in body contacted mode or floating body mode. Data can be taken in each mode and compared to extract a floating body voltage.
摘要翻译： 提供了一种用于测试浮体场效应晶体管（FET）的电路及相关方法。 本发明的实施例包括可以以浮体模式或身体接触模式操作的接触体FET结构的电路和通道FET。 接触体FET结构的主体连接到通道FET的漏极。 可以将电压施加到通道FET，以允许或限制通过通道FET的电流，以在身体接触模式或浮体模式中操作接触体FET结构。 数据可以在每种模式下进行比较，并提取浮体电压。
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3.发明授权Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations 失效使用组合二极管/电阻器结构测量电流和电阻，以监控集成电路制造工艺的变化公开(公告)号：US08709833B2
公开(公告)日：2014-04-29
申请号：US13334632
申请日：2011-12-22
CPC分类号： H01L23/58 , G01R19/0092 , G01R27/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要翻译： 使用可操作地连接到计算机化机器的制造设备，在集成电路结构内形成多个二极管/电阻器件。 每个二极管/电阻器件包括集成到单个结构中的二极管器件和电阻器件。 在使用可操作地连接到计算机化机器的测试设备来测试集成电路结构时测量每个二极管/电阻器件的电阻。 在使用测试设备的集成电路结构测试期间，也测量通过每个二极管/电阻器件的电流。 然后，根据集成电路结构内的晶体管器件的特性的变化和/或集成电路结构内的晶体管器件的制造工艺的变化来计算电阻和电流的响应曲线。
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4.发明申请MEASURING CURRENT AND RESISTANCE USING COMBINED DIODES/RESISTOR STRUCTURE TO MONITOR INTEGRATED CIRCUIT MANUFACTURING PROCESS VARIATIONS 失效使用组合二极管/电阻结构测量电流和电阻监视集成电路制造过程变化公开(公告)号：US20130161615A1
公开(公告)日：2013-06-27
申请号：US13334632
申请日：2011-12-22
CPC分类号： H01L23/58 , G01R19/0092 , G01R27/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要翻译： 使用可操作地连接到计算机化机器的制造设备，在集成电路结构内形成多个二极管/电阻器件。 每个二极管/电阻器件包括集成到单个结构中的二极管器件和电阻器件。 在使用可操作地连接到计算机化机器的测试设备来测试集成电路结构时测量每个二极管/电阻器件的电阻。 在使用测试设备的集成电路结构测试期间，也测量通过每个二极管/电阻器件的电流。 然后，根据集成电路结构内的晶体管器件的特性的变化和/或集成电路结构内的晶体管器件的制造工艺的变化来计算电阻和电流的响应曲线。
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5.发明授权Semiconductor structure incorporating multiple nitride layers to improve thermal dissipation away from a device and a method of forming the structure 有权结合了多个氮化物层以提高远离器件的散热的半导体结构和形成该结构的方法公开(公告)号：US08053870B2
公开(公告)日：2011-11-08
申请号：US12638004
申请日：2009-12-15
IPC分类号： H01L23/58
CPC分类号： H01L23/53295 , H01L23/3677 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L2224/18
摘要： Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provide improved heat dissipation away from the device. Also disclosed are embodiments of a method of forming such a semiconductor structure in conjunction with the formation of any of the following nitride layers during standard processing of other devices: a nitride hardmask layer (OP layer), a “sacrificial” nitride layer (SMT layer), a tensile nitride layer (WN layer) and/or a compressive nitride layer (WP layer). Optionally, the embodiments also incorporate incomplete contacts that extend through the blanket oxide layer into one or more of the nitride layers without contacting the device in order to further improve heat dissipation.
摘要翻译： 公开了一种半导体结构的实施例，该半导体结构包括层叠在器件的中心区域和覆盖氧化物层之间的多个氮化物层。 这些氮化物层比覆盖氧化物层更具有导热性，因此提供远离器件的改进的散热。 还公开了在其它器件的标准处理期间结合形成下列氮化物层的方法的一种方法的实施例：氮化物硬掩模层（OP层），“牺牲”氮化物层（SMT层 ），拉伸氮化物层（WN层）和/或压缩氮化物层（WP层）。 可选地，实施例还包括不完全接触，其将覆盖氧化物层延伸到一个或多个氮化物层中，而不接触该器件，以进一步改善散热。
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6.发明授权公开(公告)号：US08470682B2
公开(公告)日：2013-06-25
申请号：US12968001
申请日：2010-12-14
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L23/5228 , H01L27/016 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor structure includes forming at least one trench in an insulator layer formed on a substrate. A distance between a bottom edge of the at least one trench and a top surface of a substrate is shorter than a distance between an uppermost surface of the insulator layer and the top surface of the substrate. The method also includes: forming a resistor on the insulator layer and extending into the at least one trench; forming a first contact in contact with the resistor; and forming a second contact in contact with the resistor such that current is configured to flow from the first contact to the second contact through a central portion of the resistor.
摘要翻译： 形成半导体结构的方法包括在形成在基板上的绝缘体层中形成至少一个沟槽。 所述至少一个沟槽的底部边缘与衬底的顶部表面之间的距离小于所述绝缘体层的最上表面与所述衬底的顶表面之间的距离。 该方法还包括：在绝缘体层上形成电阻并延伸到至少一个沟槽中; 形成与所述电阻器接触的第一触点; 以及形成与所述电阻器接触的第二触点，使得电流被配置为通过所述电阻器的中心部分从所述第一触点流过所述第二触点。
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7.发明授权Butted SOI junction isolation structures and devices and method of fabrication 有权对接SOI结隔离结构和器件及其制造方法公开(公告)号：US08741725B2
公开(公告)日：2014-06-03
申请号：US12943084
申请日：2010-11-10
IPC分类号： H01L29/06
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译： 一种结构，一种FET，一种制造该结构和制造该FET的方法。 该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接， 掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。
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8.发明申请BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION 有权所谓的SOI结隔离结构和装置以及制造方法公开(公告)号：US20120112280A1
公开(公告)日：2012-05-10
申请号：US12943084
申请日：2010-11-10
IPC分类号： H01L29/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译： 一种结构，一种FET，一种制造该结构和制造该FET的方法。 该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接， 掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。
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公开(公告)号：US07808039B2
公开(公告)日：2010-10-05
申请号：US12099879
申请日：2008-04-09
申请人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
发明人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
IPC分类号： H01L27/088
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/0722
摘要： A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.
摘要翻译： 绝缘体上半导体晶体管器件包括源极区，漏极区，体区和源极横向双极晶体管。 源区具有第一导电类型。 体区具有第二导电类型并且位于源区和漏区之间。 源极横向双极晶体管包括基极，集电极和发射极。 硅化物区将基底连接到收集器。 发射器是身体区域。 集电体具有第二导电类型，基极是源极区，位于发射极和集电极之间。
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公开(公告)号：US20090256204A1
公开(公告)日：2009-10-15
申请号：US12099879
申请日：2008-04-09
申请人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
发明人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
IPC分类号： H01L29/786
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/0722
摘要： A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.
摘要翻译： 绝缘体上半导体晶体管器件包括源极区，漏极区，体区和源极横向双极晶体管。 源区具有第一导电类型。 体区具有第二导电类型并且位于源区和漏区之间。 源极横向双极晶体管包括基极，集电极和发射极。 硅化物区将基底连接到收集器。 发射器是身体区域。 集电体具有第二导电类型，基极是源极区，位于发射极和集电极之间。
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