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公开(公告)号：US08637871B2
公开(公告)日：2014-01-28
申请号：US12939462
申请日：2010-11-04
IPC分类号： H01L29/15
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66659
摘要： An asymmetric hetero-structure FET and method of manufacture is provided. The structure includes a semiconductor substrate and an epitaxially grown semiconductor layer on the semiconductor substrate. The epitaxially grown semiconductor layer includes an alloy having a band structure and thickness that confines inversion carriers in a channel region, and a thicker portion extending deeper into the semiconductor structure at a doped edge to avoid confinement of the inversion carriers at the doped edge.
摘要翻译： 提供了非对称异质结构FET及其制造方法。 该结构包括在半导体衬底上的半导体衬底和外延生长的半导体层。 外延生长的半导体层包括具有限制沟道区域中的反转载流子的带结构和厚度的合金，以及在掺杂边缘处更深地延伸到半导体结构中的较厚部分，以避免在掺杂边缘处限制反转载流子。
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公开(公告)号：US07473605B2
公开(公告)日：2009-01-06
申请号：US11866435
申请日：2007-10-03
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.
摘要翻译： 公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。 厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。 为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。
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公开(公告)号：US07326976B2
公开(公告)日：2008-02-05
申请号：US11164216
申请日：2005-11-15
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.
摘要翻译： 公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。 厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。 为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。
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4.发明授权Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations 失效使用组合二极管/电阻器结构测量电流和电阻，以监控集成电路制造工艺的变化公开(公告)号：US08709833B2
公开(公告)日：2014-04-29
申请号：US13334632
申请日：2011-12-22
CPC分类号： H01L23/58 , G01R19/0092 , G01R27/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要翻译： 使用可操作地连接到计算机化机器的制造设备，在集成电路结构内形成多个二极管/电阻器件。 每个二极管/电阻器件包括集成到单个结构中的二极管器件和电阻器件。 在使用可操作地连接到计算机化机器的测试设备来测试集成电路结构时测量每个二极管/电阻器件的电阻。 在使用测试设备的集成电路结构测试期间，也测量通过每个二极管/电阻器件的电流。 然后，根据集成电路结构内的晶体管器件的特性的变化和/或集成电路结构内的晶体管器件的制造工艺的变化来计算电阻和电流的响应曲线。
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5.发明申请MEASURING CURRENT AND RESISTANCE USING COMBINED DIODES/RESISTOR STRUCTURE TO MONITOR INTEGRATED CIRCUIT MANUFACTURING PROCESS VARIATIONS 失效使用组合二极管/电阻结构测量电流和电阻监视集成电路制造过程变化公开(公告)号：US20130161615A1
公开(公告)日：2013-06-27
申请号：US13334632
申请日：2011-12-22
CPC分类号： H01L23/58 , G01R19/0092 , G01R27/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要翻译： 使用可操作地连接到计算机化机器的制造设备，在集成电路结构内形成多个二极管/电阻器件。 每个二极管/电阻器件包括集成到单个结构中的二极管器件和电阻器件。 在使用可操作地连接到计算机化机器的测试设备来测试集成电路结构时测量每个二极管/电阻器件的电阻。 在使用测试设备的集成电路结构测试期间，也测量通过每个二极管/电阻器件的电流。 然后，根据集成电路结构内的晶体管器件的特性的变化和/或集成电路结构内的晶体管器件的制造工艺的变化来计算电阻和电流的响应曲线。
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公开(公告)号：US20120105095A1
公开(公告)日：2012-05-03
申请号：US12938440
申请日：2010-11-03
IPC分类号： G01R31/26
CPC分类号： H01L22/32 , G01R31/2621 , G01R31/2644 , G01R31/2884 , H01L22/34 , H01L27/1203 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： A circuit for testing a floating body field-effect transistor (FET), and a related method, are provided. Embodiments of this invention include a circuit including a contacted-body FET structure that can be operated in a floating body mode or a body-contacted mode, and a passgate FET. A body of the contacted-body FET structure is connected to the drain of the passgate FET. Voltage can be applied to the passgate FET to either allow or restrict current flow through the passgate FET, to operate the contacted-body FET structure in body contacted mode or floating body mode. Data can be taken in each mode and compared to extract a floating body voltage.
摘要翻译： 提供了一种用于测试浮体场效应晶体管（FET）的电路及相关方法。 本发明的实施例包括可以以浮体模式或身体接触模式操作的接触体FET结构的电路和通道FET。 接触体FET结构的主体连接到通道FET的漏极。 可以将电压施加到通道FET，以允许或限制通过通道FET的电流，以在身体接触模式或浮体模式中操作接触体FET结构。 数据可以在每种模式下进行比较，并提取浮体电压。
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7.发明授权Semiconductor devices having tensile and/or compressive stress and methods of manufacturing 有权具有拉伸和/或压缩应力的半导体器件和制造方法公开(公告)号：US09368410B2
公开(公告)日：2016-06-14
申请号：US12033280
申请日：2008-02-19
IPC分类号： H01L29/78 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76205 , H01L21/823878 , H01L29/7846
摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
摘要翻译： 公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。 该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。 该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。 第一氧化沟槽在通道中产生应变分量以增加器件性能。
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公开(公告)号：US08617412B2
公开(公告)日：2013-12-31
申请号：US12966370
申请日：2010-12-13
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译： 本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。 纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。 纳米线结构可以包括多个垂直堆叠的水平纳米线。
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9.发明授权公开(公告)号：US08609453B2
公开(公告)日：2013-12-17
申请号：US12951601
申请日：2010-11-22
IPC分类号： H01L21/00
CPC分类号： H01L31/186 , H01L31/0248 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The method further includes forming openings in the monocrystalline silicon layer, and detaching the monocrystalline silicon layer from the substrate by selectively etching the intermediate layer through the openings.
摘要翻译： 描述了可重复使用的基板和用于形成单晶硅太阳能电池的方法。 形成光伏电池的方法包括在单晶硅衬底上形成中间层，在中间层上形成单晶硅层，并在单晶硅层中形成电特征。 该方法还包括在单晶硅层中形成开口，并且通过选择性地通过开口蚀刻中间层，从而将单晶硅层从衬底上分离出来。
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10.发明申请CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD 审中-公开用于修改半导体器件中的应力的接触棒及相关方法公开(公告)号：US20130240997A1
公开(公告)日：2013-09-19
申请号：US13424319
申请日：2012-03-19
IPC分类号： H01L27/11 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823871 , H01L27/1104 , H01L29/7843
摘要： Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.
摘要翻译： 公开了用于形成应力优化接触棒和触点的解决方案。 一方面，公开了一种具有源极/漏极区域的n型场效应晶体管（NFET）的半导体器件; 具有源极/漏极区域的p型场效应晶体管（PFET） 在NFET和PFET两者上的应力诱导层，应力诱导层仅引起压缩应力和拉伸应力之一; 接触棒延伸穿过应力感应层并且耦合到PFET和NFET的所选器件的源/漏区中的至少一个，以修改与在另一器件中感应的应力相比在所选器件中感应的应力; 以及延伸穿过应力感应层并且耦合到PFET和NFET的另一个器件的源极/漏极区域中的至少一个的圆形接触。
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