公开(公告)号：US4939640A

公开(公告)日：1990-07-03

申请号：US597195

申请日：1984-04-05

申请人： Brett L. Bachman ,  Richard A. Belgard ,  Richard G. Bratt ,  Thomas M. Jones

发明人： Brett L. Bachman ,  Richard A. Belgard ,  Richard G. Bratt ,  Thomas M. Jones

IPC分类号： G06F9/22

CPC分类号： G06F9/223

摘要： A data processing system which includes a memory and a processor comprising at least two execution units. The system further includes a microcode control unit for storing sequences of microinstructions and an execution microinstruction stack containing at least one stack frame containing the machine state of a first execution unit when the execution of a microinstruction has been interrupted. A memory microinstruction stack is provided to store a plurality of stack frames, stack frames being transferrable between the execution microinstruction stack and the memory microinstructiion stack. The microcode control unit contains sequences of monitor microinstructions and has associated with it a minotor microinstruction stack for storing the machine state of the first execution unit when the execution of a monitor microinstruction has been interrupted. A second execution unit for executing primarily arithmetic microinstructions includes an execution storage unit containing the current machine state of the second execution unit and an arithmetic stack which stores the machine state of the second execution unit when it has executed a previous arithmetic microinstruction. The memory includes a memory arithmetic stack containing further arithmetic stack frames, stack frames being transferrable between the execution storage unit and the memory arithmetic stack. Further an instruction stack is provided for storing the machine state in the processor when execution of a macroinstruction has been interrupted.

摘要翻译： 一种包括存储器和包括至少两个执行单元的处理器的数据处理系统。 所述系统还包括微代码控制单元，用于存储微指令序列和执行微指令栈，所述执行微指令栈包含至少一个堆栈帧，所述至少一个堆栈帧在微指令的执行已中断时包含第一执行单元的机器状态。 提供存储器微指令堆栈以存储多个堆栈帧，堆栈帧可在可执行微指令栈和存储器微指令栈之间传送。 微代码控制单元包含监视器微指令的序列，并且与监视器微指令相关联，当监视器微指令的执行已被中断时，用于存储第一执行单元的机器状态的微运动微指令堆栈。 用于主要执行算术微指令的第二执行单元包括执行存储单元，其包含第二执行单元的当前机器状态，以及算术堆栈，当执行了先前的算术微指令时，存储第二执行单元的机器状态。 存储器包括存储器运算堆栈，其包含进一步的算术堆栈帧，堆栈帧可在执行存储单元和存储器运算堆栈之间传输。 此外，提供了用于在执行宏指令已被中断时将处理器状态存储在处理器中的指令堆栈。

公开(公告)号：US4445177A

公开(公告)日：1984-04-24

申请号：US266411

申请日：1981-05-22

申请人： Richard G. Bratt ,  Stephen I. Schleimer ,  John F. Pilat ,  Richard A. Belgard ,  Steven J. Wallach ,  Gerald F. Clancy ,  Craig J. Mundie ,  David H. Bernstein ,  Edward S. Gavrin ,  Thomas M. Jones ,  Brett L. Bachman

发明人： Richard G. Bratt ,  Stephen I. Schleimer ,  John F. Pilat ,  Richard A. Belgard ,  Steven J. Wallach ,  Gerald F. Clancy ,  Craig J. Mundie ,  David H. Bernstein ,  Edward S. Gavrin ,  Thomas M. Jones ,  Brett L. Bachman

IPC分类号： G06F9/45 ,  G06F9/22

CPC分类号： G06F8/41

摘要： A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique indentification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described withreference to the invention herein, indentify locations of object information to be accessed by utilizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format. Arithmetic logic unit (ALU) means, also as particularly described with reference to the invention herein, include general register means having three vertically oriented parts for storing such respective fields. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

公开(公告)号：US4499535A

公开(公告)日：1985-02-12

申请号：US266427

申请日：1981-05-22

申请人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Craig J. Mundie ,  James T. Nealon ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach

发明人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Craig J. Mundie ,  James T. Nealon ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach

IPC分类号： G06F9/318 ,  G06F9/34 ,  G06F7/04

CPC分类号： G06F9/30192 ,  G06F9/34

摘要： A digital computer uses a memory which is structured into objects, which are blocks of storage of arbitrary length, in which data items are accessed by descriptors which for a desired data item specify the object, the offset into that object, and the length of the data object. The computer system of the present invention further provides the ability to execute any of a plurality of dialects of internal instructions, the repertoire of such dialects being virtually infinite, since there is the ability to load a supporting microcode during operation as needed.

摘要翻译： 数字计算机使用被构造成对象的存储器，该对象是任意长度的存储块，其中通过描述符访问数据项，对于期望的数据项指定对象，到该对象的偏移量以及该对象的长度 数据对象。 本发明的计算机系统进一步提供执行内部指令的多个方言中的任何一种方式的能力，这种方言的曲目几乎是无限的，因为在需要时可以在运行期间加载支持的微代码。

公开(公告)号：US4498131A

公开(公告)日：1985-02-05

申请号：US266408

申请日：1981-05-22

申请人： Richard G. Bratt ,  Edward S. Gavrin ,  Stephen I. Schleimer ,  John F. Pilat ,  Walter A. Wallach, Jr. ,  Michael S. Richmond ,  Richard A. Belgard ,  David A. Farber ,  John K. Ahlstrom ,  Steven J. Wallach ,  Lawrence H. Katz ,  Douglas M. Wells ,  Craig J. Mundie ,  Gerald F. Clancy ,  David H. Bernstein ,  Thomas M. Jones ,  Brett L. Bachman

发明人： Richard G. Bratt ,  Edward S. Gavrin ,  Stephen I. Schleimer ,  John F. Pilat ,  Walter A. Wallach, Jr. ,  Michael S. Richmond ,  Richard A. Belgard ,  David A. Farber ,  John K. Ahlstrom ,  Steven J. Wallach ,  Lawrence H. Katz ,  Douglas M. Wells ,  Craig J. Mundie ,  Gerald F. Clancy ,  David H. Bernstein ,  Thomas M. Jones ,  Brett L. Bachman

IPC分类号： G01R31/3185 ,  G06F7/00 ,  G06F7/57 ,  G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/35 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07 ,  G06F12/08 ,  G06F12/14

CPC分类号： G01R31/318505 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/0875 ,  G06F12/1483 ,  G06F7/00 ,  G06F7/483 ,  G06F9/3013 ,  G06F9/35 ,  G06F9/4843 ,  G06F9/54 ,  G06F7/49905 ,  G06F7/4991 ,  G06F7/49926

摘要： A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system utilizes unique addressing mechanisms the addresses of which have object fields, offset fields and length fields for specifying the location and the total number of bits of an addressed object. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing the user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object.

摘要翻译： 数字数据处理系统具有被组织成至少包含操作数和指令的对象的存储器。 每个对象由识别数据处理系统和对象的唯一且永久的标识符代码来标识。 该系统利用独特的寻址机制，其地址具有用于指定寻址对象的位置和总位数的对象字段，偏移字段和长度字段。 该系统使用保护技术来防止由识别用户的主题号码，用于执行用户过程的系统的处理以及由该用户执行的系统的操作类型由用户标识的用户的未经授权的访问 用户程序。 每个对象的访问控制列表包括具有对对象的访问权限的每个对象的访问控制列表条目，以及用于在允许访问对象之前确认特定活动主体具有对特定对象的访问权限的装置。

公开(公告)号：US4480306A

公开(公告)日：1984-10-30

申请号：US266425

申请日：1981-05-22

申请人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

发明人： Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  John F. Pilat ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

IPC分类号： G06F9/26 ,  G06F9/22

CPC分类号： G06F9/26

摘要： A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described with reference to the invention herein, identify locations of object information to be accessed by utlizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format. Arithmetic logic unit (ALU) means, also as particularly described with reference to the invention herein, include general register means having three vertically oriented parts for storing such respective fields. Such ALU means further include an ALU microinstruction stack means having at least one microinstruction stack frame for storing the state of execution of a microinstruction. A memory microinstruction stack is provided to store a plurality of microinstruction stack frames so that microinstruction stack frames can be transferred between the ALU and the memory microinstruction stacks. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

公开(公告)号：US4498132A

公开(公告)日：1985-02-05

申请号：US266413

申请日：1981-05-22

申请人： John K. Ahlstrom ,  Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  Michael S. Richmond ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

发明人： John K. Ahlstrom ,  Brett L. Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Gerald F. Clancy ,  Edward S. Gavrin ,  Ronald H. Gruner ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  Michael S. Richmond ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr. ,  Douglas M. Wells

IPC分类号： G01R31/3185 ,  G06F7/00 ,  G06F7/57 ,  G06F9/22 ,  G06F9/26 ,  G06F9/318 ,  G06F9/35 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07 ,  G06F12/08 ,  G06F12/14

CPC分类号： G06F9/54 ,  G01R31/318505 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/0875 ,  G06F12/1483 ,  G06F7/00 ,  G06F7/483 ,  G06F9/223 ,  G06F9/226 ,  G06F9/262 ,  G06F9/268 ,  G06F9/3017 ,  G06F9/35 ,  G06F9/4843 ,  G06F7/49905 ,  G06F7/4991 ,  G06F7/49926

摘要： A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system further uses multilevel microcode techniques for controlling sequences of microinstructions and for controlling the interval operations of the processor. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing a user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object. The system also includes stacks for containing information relating to the current state of execution of the system.

摘要翻译： 数字数据处理系统具有被组织成至少包含操作数和指令的对象的存储器。 每个对象由识别数据处理系统和对象的唯一且永久的标识符代码来标识。 该系统还使用多级微代码技术来控制微指令的序列并且用于控制处理器的间隔操作。 该系统使用保护技术来防止由标识用户的主题号码，用于执行用户过程的系统的处理以及由该用户执行的系统的操作类型由用户标识的用户的未经授权的访问 用户程序。 每个对象的访问控制列表包括具有对对象的访问权限的每个对象的访问控制列表条目，以及用于在允许访问对象之前确认特定活动主体具有对特定对象的访问权限的装置。 系统还包括用于包含与系统的当前执行状态有关的信息的堆栈。

公开(公告)号：US4493023A

公开(公告)日：1985-01-08

申请号：US266403

申请日：1981-05-22

申请人： Edward S. Gavrin ,  Richard G. Bratt ,  Stephen I. Schleimer ,  John F. Pilat ,  Michael S. Richmond ,  Walter A. Wallach, Jr. ,  Richard A. Belgard ,  David A. Farber ,  John K. Ahlstrom ,  Steven J. Wallach ,  Gerald F. Clancy ,  Craig J. Mundie ,  Thomas M. Jones ,  Brett L. Bachman ,  David H. Bernstein

发明人： Edward S. Gavrin ,  Richard G. Bratt ,  Stephen I. Schleimer ,  John F. Pilat ,  Michael S. Richmond ,  Walter A. Wallach, Jr. ,  Richard A. Belgard ,  David A. Farber ,  John K. Ahlstrom ,  Steven J. Wallach ,  Gerald F. Clancy ,  Craig J. Mundie ,  Thomas M. Jones ,  Brett L. Bachman ,  David H. Bernstein

IPC分类号： G01R31/3185 ,  G06F7/00 ,  G06F7/57 ,  G06F9/22 ,  G06F9/26 ,  G06F9/35 ,  G06F9/46 ,  G06F9/48 ,  G06F11/07 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30

CPC分类号： G06F11/0793 ,  G01R31/318505 ,  G06F11/0721 ,  G06F11/073 ,  G06F12/0875 ,  G06F12/1483 ,  G06F7/00 ,  G06F7/483 ,  G06F9/223 ,  G06F9/226 ,  G06F9/262 ,  G06F9/268 ,  G06F9/35 ,  G06F9/4843 ,  G06F9/54 ,  G06F7/49905 ,  G06F7/4991 ,  G06F7/49926

摘要： A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

摘要翻译： 具有灵活的内部结构的数据处理系统，具有多层次的控制和堆栈机制以及执行多个并发操作的能力，并向用户提供灵活的简化界面，保护用户不受任何用户的影响。 该系统内部由多个独立的独立处理器组成，每个独立的处理器具有单独的微指令控制和至少一个独立于中央通信和存储器节点的独立端口。 通信和存储器节点是具有独立且独立的微指令控制的独立处理器，并且包括能够执行多个并发存储器和通信操作的多个独立操作的微指令控制的处理器。 寻址机制允许永久，唯一的信息识别和所有这些系统可访问和共同的极大的地址空间。 地址与系统物理配置无关。 信息被识别为细粒度级别和信息类型和格式。 保护机制提供与个体信息相关联的可变访问权限。 用户语言指令被转换为方言编码的，统一的中间级指令，以便为所有用户语言提供相同的执行功能。 操作数由统一格式名称引用，通过对用户透明的内部机制转换为地址。

公开(公告)号：US4455604A

公开(公告)日：1984-06-19

申请号：US266422

申请日：1981-05-22

申请人： John K. Ahlstrom ,  Brett Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Ronald H. Gruner ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  Michael S. Richmond ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr ,  Douglas M. Well

发明人： John K. Ahlstrom ,  Brett Bachman ,  Richard A. Belgard ,  David H. Bernstein ,  Richard G. Bratt ,  Ronald H. Gruner ,  Thomas M. Jones ,  Lawrence H. Katz ,  Craig J. Mundie ,  Michael S. Richmond ,  Stephen I. Schleimer ,  Steven J. Wallach ,  Walter A. Wallach, Jr ,  Douglas M. Well

IPC分类号： G06F9/44 ,  G06F7/00 ,  G06F9/10

CPC分类号： G06F9/4428

摘要： The processor of the present invention executes procedures, which comprise S-language instructions and names. S-languages are of higher order than typical machine languages and can be tailored to user high-order languages. Each procedure includes a dialect code which the processor interprets, enabling it to execute any of a plurality of dialects of S-languages. The processor includes means for resolving names into operand logical addresses. The processor possosses multiple levels of microcode control means, each with its own set of stacks.

摘要翻译： 本发明的处理器执行包括S语言指令和名称的过程。 S语言比典型的机器语言高，可以根据用户高阶语言进行定制。 每个过程包括处理器解释的方言代码，使其能够执行S语言的多个方言中的任何一种。 处理器包括用于将名称解析为操作数逻辑地址的装置。 处理器可以处理多个级别的微码控制装置，每一个都有自己的一组堆栈。

公开(公告)号：US4514800A

公开(公告)日：1985-04-30

申请号：US266525

申请日：1981-05-22

申请人： Ronald H. Gruner ,  Gerald F. Clancy ,  Craig J. Mundie ,  Steven J. Wallach ,  Stephen I. Schleimer ,  Walter A. Wallach, Jr. ,  John K. Ahlstrom ,  David H. Bernstein ,  Michael S. Richmond ,  David A. Farber ,  John F. Pilat ,  Richard A. Belgard ,  Richard G. Bratt

发明人： Ronald H. Gruner ,  Gerald F. Clancy ,  Craig J. Mundie ,  Steven J. Wallach ,  Stephen I. Schleimer ,  Walter A. Wallach, Jr. ,  John K. Ahlstrom ,  David H. Bernstein ,  Michael S. Richmond ,  David A. Farber ,  John F. Pilat ,  Richard A. Belgard ,  Richard G. Bratt

IPC分类号： G06F9/35 ,  G06F9/40 ,  G06F13/00

CPC分类号： G06F9/4425 ,  G06F9/35

摘要： A digital computer system including a memory and a processor. The memory operates in response to memory commands received from the processor. Items of data stored in the memory include instructions to which the processor responds. Each instruction contains an operation code which belongs to one of several sets of operation codes. The meaning of a given operation code is determined by the operation code set to which the instruction belongs. Some of the instructions also contain names representing items of data used in the operation specified by the operation code. The processor includes an operation code decoding system which decodes the operation code as required for the instruction set to which it belongs, a name resolution system for deriving the address of the data item represented by a name from the name using an architectural base address contained in the name resolution system, and a control system which controls the operation of the processor. The processor performs a call operation and a return operation. Only the call operation and the return operation may change the current architectural base address. The memory further contains name table entries associated with the names. Each name table entry contains information used by the name resolution system when it resolves a name.

摘要翻译： 一种包括存储器和处理器的数字计算机系统。 存储器响应于从处理器接收的存储器命令而工作。 存储在存储器中的数据项包括处理器响应的指令。 每条指令都包含一个操作码，它属于几组操作码之一。 给定操作代码的含义由指令所属的操作代码集确定。 一些指令还包含表示由操作代码指定的操作中使用的数据项的名称。 该处理器包括操作码解码系统，该系统根据其所属的指令集的需要对操作码进行解码，一个名称解析系统，用于从名称中导出由名称所代表的数据项的地址， 名称解析系统和控制处理器的操作的控制系统。 处理器执行呼叫操作和返回操作。 只有通话操作和返回操作才能更改当前的架构基地址。 内存还包含与名称相关联的名称表条目。 每个名称表项包含名称解析系统在解析名称时使用的信息。

公开(公告)号：US4803619A

公开(公告)日：1989-02-07

申请号：US877699

申请日：1986-06-20

申请人： David H. Bernstein ,  Walter A. Wallach ,  Michael S. Richmond ,  John K. Ahlstrom ,  John F. Pilat ,  David A. Farber ,  Richard A. Belgard ,  Richard G. Bratt

发明人： David H. Bernstein ,  Walter A. Wallach ,  Michael S. Richmond ,  John K. Ahlstrom ,  John F. Pilat ,  David A. Farber ,  Richard A. Belgard ,  Richard G. Bratt

IPC分类号： G06F9/35 ,  G06F9/355 ,  G06F9/42 ,  G06F13/00 ,  G06F9/00

CPC分类号： G06F9/342 ,  G06F9/35 ,  G06F9/4426

摘要： Apparatus in a digital computer system capable of performing a call operation and a return operation for obtaining addresses of data from names representing the data. Each name is permanently associated with a procedure containing instructions to which the digital computer system responds. Each name further corresponds to a name table entry which is permanently associated with the same procedure. The corresponding name table entry for a name specifies how a base address and a displacement are to be derived using a plurality of current base addresses. The values of these addresses change only when the computer system executes a call operation suspending a current execution of a procedure and commencing another current execution or a return operation terminating the current execution and resuming the execution which was suspended to commence the terminated execution. The operation of resolving a name, i.e., obtaining the address of the data represented by the name, is performed by name interpretation apparatus in processors of the data processing system. In response to a name, the name interpretation apparatus locates the name table entry corresponding to the name fetches the name table entry, calculates the base address and the displacement using the name table entry and the current architectural base addresses, and then adds the base address to the displacement to obtain the address of the data represented by the name.

摘要翻译： 能够执行呼叫操作和返回操作的数字计算机系统中的装置，用于从表示数据的名称获得数据的地址。 每个名称与包含数字计算机系统响应的指令的过程永久关联。 每个名称进一步对应于与相同过程永久关联的名称表条目。 名称的相应名称表项指定如何使用多个当前基地址来导出基地址和位移。 这些地址的值只有在计算机系统执行暂停执行过程的当前执行的调用操作并且开始当前执行的另一个当前执行或返回操作终止当前执行并且恢复被暂停的执行以开始终止执行时才改变。 通过名称解释装置在数据处理系统的处理器中执行解析名称的操作，即获得由该名称表示的数据的地址。 响应于名称，名称解释装置找到与名称相对应的名称表条目，获取名称表项，使用名称表项和当前架构基地址来计算基地址和位移，然后添加基地址 以位移获取由名称表示的数据的地址。