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公开(公告)号：US06279072B1
公开(公告)日：2001-08-21
申请号：US09359926
申请日：1999-07-22
IPC分类号： G06F1200
CPC分类号： G06F11/1052
摘要： A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.
摘要翻译： 存储器结构包括分为低阶存储体和高阶存储体的存储器模块。 低阶存储体用作常规存储器。 根据数据的路由，高阶存储体被用作常规存储器或ECC存储器。 在一个实施例中，当高阶存储体用作常规存储器时，来自高阶存储体的数据经由主多路复用器被路由到数据总线。 当高阶存储体用作ECC存储器时，来自辅助部分的数据通过主复用器被路由到纠错电路。 辅助复用器将来自模块的辅助部分的ECC位或主板上的专用ECC存储器组合。 因此，辅助部分补充了板载ECC存储器，以便为需要纠错的错误不耐受应用提供有效的更大的ECC存储器的支持。
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公开(公告)号：US6094702A
公开(公告)日：2000-07-25
申请号：US960854
申请日：1997-10-30
CPC分类号： G06F21/79
摘要： An application-specific integrated circuit (ASIC) for enabling access to memory. ASIC includes a decryptor, a valid authorization storage component, an upgrade verifier, an upgrade storage component, and an enabling component. The decryptor inputs an encrypted authorization code and outputs a decrypted authorization code. The valid authorization storage component stores and outputs a valid authorization code. The upgrade verifier inputs the decrypted authorization code and the valid authorization code, compares the decrypted authorization code to the valid authorization code to determine whether access to the portion of memory is authorized, and outputs a signal to enable access to the portion of memory. The upgrade storage component stores the signal output from the upgrade verifier. The enabling component inputs a memory access signal and a signal stored in the upgrade storage component and outputs a signal indicating whether the portion of memory is enabled.
摘要翻译： 专用集成电路（ASIC），用于访问存储器。 ASIC包括解密器，有效的授权存储组件，升级验证器，升级存储组件和启用组件。 解密器输入加密的授权码并输出解密的授权码。 有效的授权存储组件存储并输出有效的授权码。 升级验证者输入解密的授权码和有效的授权码，将解密的授权码与有效的授权码进行比较，以确定对存储器部分的访问是否被授权，并输出一个信号，以便访问存储器的一部分。 升级存储组件存储从升级验证器输出的信号。 启用组件输入存储器访问信号和存储在升级存储组件中的信号，并输出指示存储器部分是否被使能的信号。
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公开(公告)号：US06584543B2
公开(公告)日：2003-06-24
申请号：US10295661
申请日：2002-11-14
IPC分类号： G06F1200
CPC分类号： G06F11/1052
摘要： A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.
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公开(公告)号：US06397290B1
公开(公告)日：2002-05-28
申请号：US09932242
申请日：2001-08-17
IPC分类号： G06F1200
CPC分类号： G06F11/1052
摘要： A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.
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公开(公告)号：US10141314B2
公开(公告)日：2018-11-27
申请号：US13397392
申请日：2012-02-15
IPC分类号： H01L27/105 , G11C5/04 , H01L25/065
摘要： A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a first type and a signal presence detect unit configured to provide configuration data associated with a memory package of a second type to the memory controller. The configuration data may be used to configure the memory controller to interface with the memory package of a first type.
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公开(公告)号：US06615325B2
公开(公告)日：2003-09-02
申请号：US08984561
申请日：1997-12-03
IPC分类号： G06F1200
CPC分类号： G11C7/1027 , G11C7/1015 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/20
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs. Additionally, a DRAM is provided having both pipelined and burst Extended Data Out modes of operation and the ability to switch between them.
摘要翻译： 集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器并初始化设备以进行另一个突发访问。 该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。 此外，提供具有流水线和突发扩展数据输出操作模式的DRAM以及在它们之间切换的能力。
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公开(公告)号：US5850368A
公开(公告)日：1998-12-15
申请号：US922194
申请日：1997-09-02
CPC分类号： G11C8/04
摘要： A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.
摘要翻译： 由两个触发器和多路复用器组成的计数器产生顺序或交错地址序列。 所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。 与序列选择信号组合的输入地址被逻辑地组合以产生多路复用器选择输入，其选择第一触发器的真实和补码输出以耦合到第二触发器的输入以指定第二触发器的切换条件 。 将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化用于另一个突发存取的设备。 在脉冲串访问期间读/写控制线的转换将终止脉冲串访问并初始化设备以进行另一个突发存取。
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8.发明授权Memory device for burst or pipelined operation with mode selection circuitry 失效用于脉冲串或流水线操作的存储器件，具有模式选择电路公开(公告)号：US07124256B1
公开(公告)日：2006-10-17
申请号：US08984562
申请日：1997-12-03
CPC分类号： G11C7/1027 , G11C7/1015 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/20
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs. Additionally, a DRAM is provided having both pipelined and burst Extended Data Out modes of operation and the ability to switch between them.
摘要翻译： 集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器并初始化设备以进行另一个突发访问。 该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。 此外，提供具有流水线和突发扩展数据输出操作模式的DRAM以及在它们之间切换的能力。
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公开(公告)号：US07103742B1
公开(公告)日：2006-09-05
申请号：US08984560
申请日：1997-12-03
IPC分类号： G06F13/00
CPC分类号： G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C8/06 , G11C11/408
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs. Additionally, a DRAM is provided having both pipelined and burst Extended Data Out modes of operation and the ability to switch between them. Additionally, a memory device switchable between a patterned and a patternless addressing scheme is provided.
摘要翻译： 集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器并初始化设备以进行另一个突发访问。 该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。 此外，提供具有流水线和突发扩展数据输出操作模式的DRAM以及在它们之间切换的能力。 另外，提供了可在图案化和无图案寻址方案之间切换的存储器件。
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公开(公告)号：US5696732A
公开(公告)日：1997-12-09
申请号：US754780
申请日：1996-11-21
申请人： Paul S. Zagar , Brett L. Williams
发明人： Paul S. Zagar , Brett L. Williams
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/109 , G06F12/0638 , G11C11/407 , G11C7/1018 , G11C7/1021 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G06F2212/2022
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
摘要翻译： 集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器并初始化设备以进行另一个突发访问。 该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。
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