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14 条记录 (耗时 0.017 秒)

    Reconfigurable memory with selectable error correction storage
    1.
    发明授权
    Reconfigurable memory with selectable error correction storage 有权

    公开(公告)号：US06584543B2

    公开(公告)日：2003-06-24

    申请号：US10295661

    申请日：2002-11-14

    申请人： Brett L. Williams ,  Donald D. Baldwin

    发明人： Brett L. Williams ,  Donald D. Baldwin

    IPC分类号： G06F1200

    CPC分类号： G06F11/1052

    摘要： A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.

    Reconfigurable memory with selectable error correction storage
    2.
    发明授权
    Reconfigurable memory with selectable error correction storage 有权

    公开(公告)号：US06397290B1

    公开(公告)日：2002-05-28

    申请号：US09932242

    申请日：2001-08-17

    申请人： Brett L. Williams ,  Donald D. Baldwin

    发明人： Brett L. Williams ,  Donald D. Baldwin

    IPC分类号： G06F1200

    CPC分类号： G06F11/1052

    摘要： A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.

    Interface system between composite tubing and end fittings
    6.
    发明授权
    Interface system between composite tubing and end fittings 失效
    复合管和端接头之间的接口系统

    公开(公告)号：US6042152A

    公开(公告)日：2000-03-28

    申请号：US942414

    申请日：1997-10-01

    申请人： Donald D. Baldwin ,  John A. Reigle ,  Mark D. Drey

    发明人： Donald D. Baldwin ,  John A. Reigle ,  Mark D. Drey

    IPC分类号： F16L9/12 ,  F16L47/02 ,  F16L39/02

    CPC分类号： F16L9/12 ,  F16L47/02

    摘要： An interface system between an end of a filament composite tube and a rigid interior end fitting. The system includes a plurality of traplocks having varying wall thicknesses at the bases thereof. The traplocks also have varying angles of the bearing faces thereof. A Y-shaped seal is disposed between an inboard end of the fitting and the inside of the composite tube.

    摘要翻译： 在灯丝复合管的端部和刚性内端配件之间的界面系统。 该系统包括在其基部具有变化的壁厚的多个陷阱。 陷阱也具有其轴承面的变化的角度。 Y形密封件设置在配件的内侧端和复合管的内部之间。

    Reconfigurable memory with selectable error correction storage
    9.
    发明授权
    Reconfigurable memory with selectable error correction storage 有权
    可重新配置的存储器，具有可选择的纠错存储

    公开(公告)号：US06279072B1

    公开(公告)日：2001-08-21

    申请号：US09359926

    申请日：1999-07-22

    申请人： Brett L. Williams ,  Donald D. Baldwin

    发明人： Brett L. Williams ,  Donald D. Baldwin

    IPC分类号： G06F1200

    CPC分类号： G06F11/1052

    摘要： A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.

    摘要翻译： 存储器结构包括分为低阶存储体和高阶存储体的存储器模块。 低阶存储体用作常规存储器。 根据数据的路由，高阶存储体被用作常规存储器或ECC存储器。 在一个实施例中，当高阶存储体用作常规存储器时，来自高阶存储体的数据经由主多路复用器被路由到数据总线。 当高阶存储体用作ECC存储器时，来自辅助部分的数据通过主复用器被路由到纠错电路。 辅助复用器将来自模块的辅助部分的ECC位或主板上的专用ECC存储器组合。 因此，辅助部分补充了板载ECC存储器，以便为需要纠错的错误不耐受应用提供有效的更大的ECC存储器的支持。

    Method and apparatus for enabling access to computer system resources
    10.
    发明授权
    Method and apparatus for enabling access to computer system resources 失效
    允许访问计算机系统资源的方法和装置

    公开(公告)号：US6094702A

    公开(公告)日：2000-07-25

    申请号：US960854

    申请日：1997-10-30

    申请人： Brett L. Williams ,  Donald D. Baldwin ,  Todd Farrell

    发明人： Brett L. Williams ,  Donald D. Baldwin ,  Todd Farrell

    IPC分类号： G06F21/00 ,  G06F13/00 ,  G06F12/00

    CPC分类号： G06F21/79

    摘要： An application-specific integrated circuit (ASIC) for enabling access to memory. ASIC includes a decryptor, a valid authorization storage component, an upgrade verifier, an upgrade storage component, and an enabling component. The decryptor inputs an encrypted authorization code and outputs a decrypted authorization code. The valid authorization storage component stores and outputs a valid authorization code. The upgrade verifier inputs the decrypted authorization code and the valid authorization code, compares the decrypted authorization code to the valid authorization code to determine whether access to the portion of memory is authorized, and outputs a signal to enable access to the portion of memory. The upgrade storage component stores the signal output from the upgrade verifier. The enabling component inputs a memory access signal and a signal stored in the upgrade storage component and outputs a signal indicating whether the portion of memory is enabled.

    摘要翻译： 专用集成电路（ASIC），用于访问存储器。 ASIC包括解密器，有效的授权存储组件，升级验证器，升级存储组件和启用组件。 解密器输入加密的授权码并输出解密的授权码。 有效的授权存储组件存储并输出有效的授权码。 升级验证者输入解密的授权码和有效的授权码，将解密的授权码与有效的授权码进行比较，以确定对存储器部分的访问是否被授权，并输出一个信号，以便访问存储器的一部分。 升级存储组件存储从升级验证器输出的信号。 启用组件输入存储器访问信号和存储在升级存储组件中的信号，并输出指示存储器部分是否被使能的信号。