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公开(公告)号：US06985986B2
公开(公告)日：2006-01-10
申请号：US09870447
申请日：2001-06-01
申请人： Brian Boles , Joseph W. Triece , Joshua M. Conner
发明人： Brian Boles , Joseph W. Triece , Joshua M. Conner
CPC分类号： G06F13/24
摘要： A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.
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公开(公告)号：US07203818B2
公开(公告)日：2007-04-10
申请号：US10796771
申请日：2004-03-09
申请人： Edward Brian Boles , Rodney Jay Drake , Darrel Ray Johansen , Sumit K. Mitra , Randy Yach , James Grosbach , Joshua M. Conner , Joseph W. Triece
发明人： Edward Brian Boles , Rodney Jay Drake , Darrel Ray Johansen , Sumit K. Mitra , Randy Yach , James Grosbach , Joshua M. Conner , Joseph W. Triece
CPC分类号： G06F9/30192 , G06F9/30032 , G06F9/3004 , G06F9/30101 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/321 , G06F9/325
摘要： A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.
摘要翻译： 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。 正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此，两个文件寄存器用于一些两个操作数指令。 这允许在两个寄存器之间直接移动数据，而不经过W寄存器。 因此，提高性能并减少程序内存使用。
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公开(公告)号：US07401176B2
公开(公告)日：2008-07-15
申请号：US10969513
申请日：2004-10-20
IPC分类号： G06F12/00
CPC分类号： G06F9/355 , G06F9/30134 , G06F9/35 , G06F9/4484
摘要： Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory (“RAM”). When a first address mode is used in conjunction with the address bit and the stack pointer, the location of the access RAM can be shifted in order to achieve an index of a literal offset address mode.
摘要翻译： 具有堆栈的存储器的快速访问使用地址位，堆栈指针和快速访问随机存取存储器（“RAM”）。 当与地址位和堆栈指针一起使用第一地址模式时，可以移位存取RAM的位置，以便实现字面偏移地址模式的索引。
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公开(公告)号：US06601160B2
公开(公告)日：2003-07-29
申请号：US09870448
申请日：2001-06-01
IPC分类号： G06F1576
CPC分类号： G06F9/342 , G06F9/30185 , G06F9/345 , G06F12/0284 , G06F12/109
摘要： A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.
摘要翻译： 提供了一种处理器，其具有数据存储器，该数据存储器可以以一种模式被寻址为双存储器空间，并且在另一种模式下可以被寻址为单个线性存储器空 当处理DSP指令时，存储器可能允许从数据存储器获取双重并发操作数。 然后，存储器可以动态地允许相同的存储器作为用于非DSP指令的单个线性存储器地址空间被访问。
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公开(公告)号：US07603601B2
公开(公告)日：2009-10-13
申请号：US11355619
申请日：2006-02-16
申请人： Cristian P. Masgras , Michael Pyska , Edward Brian Boles , Joseph W. Triece , Igor Wojewoda , Mei-Ling Chen
发明人： Cristian P. Masgras , Michael Pyska , Edward Brian Boles , Joseph W. Triece , Igor Wojewoda , Mei-Ling Chen
IPC分类号： G01R31/3185
CPC分类号： G01R31/31701 , G06F11/273 , G11C29/003 , G11C29/46
摘要： A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.
摘要翻译： 特殊模式键匹配比较模块具有N存储元件和特殊模式键匹配比较器。 N存储元件累积串行数据流，然后确定数字设备是否应该以普通用户模式，公共编程模式或特定专用测试模式中操作。 为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数量的N位，以显着降低错误解码的概率。 为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则可以复位特殊模式键匹配比较模块。 特殊模式键匹配数据模式可以表示正常的用户模式，公共编程模式和特定的私人制造商测试模式。
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6.发明授权Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor 失效用于在单个周期内输出间接寻址模式地址的数据指针及其方法
公开(公告)号：US6098160A
公开(公告)日：2000-08-01
申请号：US959559
申请日：1997-10-28
申请人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
发明人： Rodney J. Drake , Randy L. Yach , Igor Wojewoda , Joseph W. Triece , Brian Boles , Darrel Johansen
CPC分类号： G06F9/35
摘要： A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
摘要翻译： 一种数据指针，用于在多个间接寻址模式中选定的一个周期内在单个周期内生成间接寻址模式地址。 数据指针与处理器架构方案一起使用，该方案允许对多种寻址模式进行编码。 数据指针寄存器耦合到处理器架构方案，用于存储要在简单的间接寻址模式中使用的操作数的当前地址。 增量器被耦合到数据指针寄存器，用于以简单的间接数据寻址模式递增一个操作数的当前地址一个设定的数字，从而产生要以具有自动预压缩的间接寻址方式使用的操作数的地址。 加法器耦合到数据指针寄存器，用于将要在简单间接数据寻址模式中使用的操作数的当前地址与偏移号组合，从而生成要在具有偏移量的间接寻址模式中使用的操作数的地址。 多路复用器电路耦合到数据指针寄存器的输出，加法器的输出端和加法器的输出端，用于选择期望的间接寻址模式地址。
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公开(公告)号：US09208095B2
公开(公告)日：2015-12-08
申请号：US11928242
申请日：2007-10-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.
摘要翻译： 一种用于中央处理单元的缓存模块具有一个具有用于存储器的接口的高速缓存控制单元，与控制单元耦合的高速缓冲存储器，其中高速缓冲存储器具有多条高速缓存行，多条高速缓存行中的至少一条高速缓存行 线路具有用于存储指令或数据的地址标签位字段和相关联的存储区域，其中地址标签位字段是可读写的，并且其中高速缓存控制单元在检测到地址已被写入地址标签位字段 以启动预载功能，其中来自存储器的指令或数据从地址加载到至少一个高速缓存行中。
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公开(公告)号：US20100306457A1
公开(公告)日：2010-12-02
申请号：US12776046
申请日：2010-05-07
CPC分类号： H04L12/40013 , H04L12/4135 , H04L49/90 , H04L49/901 , H04L2012/40215
摘要： A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.
摘要翻译： 微控制器具有随机存取存储器和控制器区域网络（CAN）控制器，控制单元接收组合的CAN消息。 控制单元使用组合的CAN消息生成缓冲器描述符表条目，并将缓冲器描述符表条目存储在随机存取存储器中，并且缓冲器描述符表条目至少具有来自CAN消息的消息标识符和加载数据，以及 跟随缓冲区描述符表项。
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公开(公告)号：US20080147979A1
公开(公告)日：2008-06-19
申请号：US11928242
申请日：2007-10-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.
摘要翻译： 一种用于中央处理单元的缓存模块具有一个具有用于存储器的接口的高速缓存控制单元，与控制单元耦合的高速缓冲存储器，其中高速缓冲存储器具有多条高速缓存行，多条高速缓存行中的至少一条高速缓存行 线路具有用于存储指令或数据的地址标签位字段和相关联的存储区域，其中地址标签位字段是可读写的，并且其中高速缓存控制单元在检测到地址已被写入地址标签位字段 以启动预载功能，其中来自存储器的指令或数据从地址加载到至少一个高速缓存行中。
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公开(公告)号：US06563740B2
公开(公告)日：2003-05-13
申请号：US09951280
申请日：2001-09-13
IPC分类号： G11C1134
CPC分类号： G11C29/50004 , G11C16/04 , G11C16/3418 , G11C29/50
摘要： An electronic circuit includes a non-volatile memory on an integrated circuit that has several memory cells. The cells each have a voltage state and a gate. A gate bias circuit on the integrated circuit is coupled to the gates of the memory cells. The gate bias circuit includes at least a read voltage and a margin voltage. A detection circuit on the integrated circuit is coupled to the cells. The detection circuit includes a comparator and a reference voltage. The reference voltage and the voltage state of one of the cells are coupled to the comparator. The detection circuit includes an output generating a signal corresponding to the comparator output. The integrated circuit includes a monitor circuit. The monitor circuit is coupled to the output of the detection circuit and determines whether the voltage state of the cell transitions between application of the read and margin voltages to the gate.
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