公开(公告)号：US06205186B1

公开(公告)日：2001-03-20

申请号：US08922720

申请日：1997-09-03

申请人： Brian K. Butler ,  Gwain Bayley ,  David Hansquine ,  Edward G. Tiedemann, Jr.

发明人： Brian K. Butler ,  Gwain Bayley ,  David Hansquine ,  Edward G. Tiedemann, Jr.

IPC分类号： H04L100

CPC分类号： H04L1/0071 ,  H03M13/3961 ,  H03M13/3988 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6325 ,  H03M13/6508 ,  H03M13/6583 ,  H04L1/0054

摘要： The certainties of transmitted bits at predetermined locations in time are determine a priori. This information is then used to set the states of a Viterbi decoder to different state metrics in accordance with the certainties of the transmitted bits. High certainty of a transmitted bit results in resetting the states corresponding to that bit to a high state metric. In contrast, low certainty of a transmitted bit results in resetting the states corresponding to that bit to a low state metric. Resetting the states to different state metrics improves the decoding performance and shortens the time required to converge the decoding trellis by eliminating improbable paths.

摘要翻译： 在预定的时间点的传输比特的确定性是先验确定的。 然后，该信息用于根据发送的比特的确定性将维特比解码器的状态设置为不同的状态度量。 发送位的高确定性导致将与该位相对应的状态重置为高状态度量。 相比之下，传输位的低确定性导致将与该位相对应的状态重置为低状态度量。 将状态重置为不同的状态度量可以提高解码性能，并通过消除不可能的路径缩短融合解码网格所需的时间。

公开(公告)号：US06519297B2

公开(公告)日：2003-02-11

申请号：US09741969

申请日：2000-12-20

申请人： Brian K. Butler ,  Gwain Bayley ,  David Hansquine ,  Edward G. Tiedemann, Jr.

发明人： Brian K. Butler ,  Gwain Bayley ,  David Hansquine ,  Edward G. Tiedemann, Jr.

IPC分类号： H04L2706

CPC分类号： H04L1/0071 ,  H03M13/3961 ,  H03M13/3988 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6325 ,  H03M13/6508 ,  H03M13/6583 ,  H04L1/0054

摘要： The certainties of transmitted bits at predetermined locations in time are determined a priori. This information is then used to set the states of a Viterbi decoder to different state metrics in accordance with the certainties of the transmitted bits. High certainty of a transmitted bit results in resetting the states corresponding to that bit to a high state metric. In contrast, low certainty of a transmitted bit results in resetting the states corresponding to that bit to a low state metric. Resetting the states to different state metrics improves the decoding performance and shortens the time required to converge the decoding trellis by eliminating improbable paths.

摘要翻译： 先前确定预定位置处的发送位的确定性。 然后，该信息用于根据发送的比特的确定性将维特比解码器的状态设置为不同的状态度量。 发送位的高确定性导致将与该位相对应的状态重置为高状态度量。 相比之下，传输位的低确定性导致将与该位相对应的状态重置为低状态度量。 将状态重置为不同的状态度量可以提高解码性能，并通过消除不可能的路径缩短融合解码网格所需的时间。

公开(公告)号：US06269130B1

公开(公告)日：2001-07-31

申请号：US09129022

申请日：1998-08-04

申请人： David Hansquine

发明人： David Hansquine

IPC分类号： H03D100

CPC分类号： H03M13/4169 ,  H03M13/4107

摘要： A serial Viterbi decoder having a chainback cache is provided for use in a mobile telephone. In one embodiment described herein, the decoder includes a branch error metric block, an add-compare-select unit, and a chainback block including a chainback RAM, a full chainback cache and chainback controller circuitry. The chainback cache caches decision bits from previous process cycles such that full chainback operations need not always be performed. The chainback cache is configured to cache on all reads. With the chainback cache, significant savings in power consumption and processing time may be achieved with only a relatively modest increase in the amount of circuitry required. In another embodiment, a full chainback cache is not provided. Rather, the chainback block instead includes an L+1 bit RAM, an updown counter and a shift register configured to emulate a chainback cache. In still another embodiment, an L bit shift register is employed instead of the combination of the L+1 bit RAM and updown counter. In the various embodiments, the chainback block may be configured to perform only one chainback read in each process cycle or may be configured to perform m chainback reads in each process cycle. In still other embodiments, the chainback block is configured to perform chainback operations based on a through b reads where the cache is accessed for each read after a reads have been done until b reads have been performed or a match is obtained. In still further embodiments, the chainback block is configured to perform chainback operations over multiple process cycles rather than only a single process cycle.

摘要翻译： 具有链回缓存的串行维特比解码器被提供用于移动电话。 在本文所述的一个实施例中，解码器包括分支误差量度块，加法比较选择单元和包括链回RAM，全链回缓存和回送控制器电路的回链块。 链回缓存从先前的处理循环缓存决策位，使得不必总是执行完全的回溯操作。 链回缓存配置为在所有读取时缓存。 使用链回缓存，可以通过仅需要的电路量的相对适度的增加来实现功耗和处理时间的显着节省。 在另一个实施例中，不提供完整的回溯高速缓存。 相反，链回块代替地包括L + 1位RAM，升级计数器和配置成模拟链回缓存的移位寄存器。 在另一个实施例中，采用L位移位寄存器来代替L + 1位RAM和上升计数器的组合。 在各种实施例中，回链块可以被配置为仅在每个处理周期中执行一个链回读取，或者可以被配置为在每个处理周期中执行m链回读取。 在其他实施例中，回溯块被配置为基于通过b读取执行回溯操作，其中在读取已经完成直到b读取已经被执行或获得匹配之后，对于每次读取访问高速缓存。 在另外的实施例中，回溯块被配置为在多个处理循环上执行链回操作，而不仅仅是单个处理循环。

公开(公告)号：US06493354B1

公开(公告)日：2002-12-10

申请号：US09189710

申请日：1998-11-11

申请人： David Hansquine ,  Avneesh Agrawal

发明人： David Hansquine ,  Avneesh Agrawal

IPC分类号： H04J316

CPC分类号： G06F9/50

摘要： A resource allocator for allocating at least two different types of hardware resources for users within a communication system, wherein the system supports up to a first predetermined number of users of one particular type and a second predetermined number of users of a second particular type. The resource allocator provides a mapping of resources, either from fixed resources to shared resources or from shared resources to fixed resources, which is both cost effective and transparent to software.

摘要翻译： 一种用于为通信系统内的用户分配至少两种不同类型的硬件资源的资源分配器，其中所述系统支持高达第一特定类型的第一预定数量的用户和第二特定类型的第二预定数量的用户。 资源分配器提供从固定资源到共享资源或从共享资源到固定资源的资源映射，这对软件来说既成本有效又透明。

公开(公告)号：US20060031618A1

公开(公告)日：2006-02-09

申请号：US10851526

申请日：2004-05-20

申请人： David Hansquine ,  Muhammad Muneer

发明人： David Hansquine ,  Muhammad Muneer

IPC分类号： G06F13/14

CPC分类号： G06F13/4295

摘要： Embodiments disclosed herein address the need for interoperability between existing serial bus interfaces and a single wire bus interface. In one aspect, the output or outputs of a three wire interface are selected in a first mode and the output of one or more single wire interfaces are selected in a second mode. In another aspect, a converter takes a single wire bus and produces signals according to a three wire interface. In yet another aspect, a termination symbol is inserted in a single wire interface signal, to facilitate conversion of the signal and connection to a three wire interface. In yet another aspect, a strobe signal and/or a clock signal are generated in response to a detected start symbol. In yet another aspect, a strobe signal is deasserted and/or a clock signal is deasserted in response to a detected termination symbol.

摘要翻译： 本文公开的实施例解决了现有串行总线接口和单线总线接口之间的互操作性的需要。 一方面，在第一模式中选择三线接口的输出或输出，并且在第二模式中选择一个或多个单线接口的输出。 在另一方面，转换器采用单线总线并根据三线接口产生信号。 在另一方面，终端符号插入单线接口信号中，以便于信号和连接到三线接口的转换。 在另一方面，响应于检测到的起始符号产生选通信号和/或时钟信号。 在另一方面，响应于检测到的终止符号，选通信号被断言和/或时钟信号被断言。

公开(公告)号：US20050257109A1

公开(公告)日：2005-11-17

申请号：US10630480

申请日：2003-07-29

申请人： Roberto Averbuj ,  David Hansquine

发明人： Roberto Averbuj ,  David Hansquine

IPC分类号： G11C29/16 ,  G01R31/28

CPC分类号： G11C29/16

摘要： A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers interpret the commands in accordance with a command protocol and generate sequences of memory operations. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands. The command protocol allows powerful algorithms to be described in an extremely concise manner that may be applied to memory modules having diverse characteristics.

摘要翻译： 描述了具有分布式算法解释的内置自检（BIST）架构。 该架构包括三层抽象层次：集中式BIST控制器，一组排序器和一组存储器接口。 BIST控制器存储一组命令，通常定义用于测试存储器模块的算法，而不考虑存储器模块的物理特性或时序要求。 顺控程序根据命令协议解释命令并生成序列的存储器操作。 存储器接口根据存储器模块的物理特性将存储器操作应用于存储器模块，例如通过基于存储器模块的行列排列来转换地址和数据信号，以实现由命令描述的位模式。 命令协议允许以非常简洁的方式描述强大的算法，其可以应用于具有不同特征的存储器模块。

公开(公告)号：US06366600B1

公开(公告)日：2002-04-02

申请号：US09211989

申请日：1998-12-14

申请人： Avneesh Agrawal ,  David Hansquine ,  Paul E. Bender

发明人： Avneesh Agrawal ,  David Hansquine ,  Paul E. Bender

IPC分类号： H04B169

CPC分类号： H04L27/0008 ,  H04B1/707

摘要： A spreader architecture for direct sequence spread spectrum communications is disclosed. This single architecture can perform OOK, BPSK, or QPSK spreading modulation of a carrier. In the QPSK and BPSK modes, input data is spread by pseudonoise signals to produce digital representations of phase-modulated baseband in-phase and quadrature components. In the OOK mode, the spectrum of the baseband components is selectively spread according to the input data. In an exemplary application, the various modulation modes are used to encode the control and traffic channels of a code-division multiple-access cellular telephone system.

摘要翻译： 公开了一种用于直接序列扩频通信的扩展器架构。 该单一架构可以执行载波的OOK，BPSK或QPSK扩展调制。 在QPSK和BPSK模式中，输入数据通过伪噪声信号进行扩展，以产生相位调制的基带同相和正交分量的数字表示。 在OOK模式中，根据输入数据选择性地扩展基带分量的频谱。 在示例性应用中，各种调制模式用于对码分多址蜂窝电话系统的控制和业务信道进行编码。

公开(公告)号：US20050259609A1

公开(公告)日：2005-11-24

申请号：US10851787

申请日：2004-05-20

申请人： David Hansquine ,  Brett Walker ,  Muhammad Muneer

发明人： David Hansquine ,  Brett Walker ,  Muhammad Muneer

IPC分类号： H04L12/40 ,  H04L12/413 ,  H04L12/50

CPC分类号： H04L12/40013 ,  H04L12/403

摘要： Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices.

摘要翻译： 本文公开的实施例解决了对单个有线总线接口的需要。 在一个方面，一种设备通过单线总线与第二设备通信，该驱动器用于使用包括起始符号，写指示符符号，地址和数据符号的写入帧来驱动总线。 在另一方面，设备在读取帧期间在单线总线上接收一个或多个数据符号。 在另一方面，一种设备通过单线总线与第二设备通信，该接收机用于在单线总线上接收包括开始符号，写指示符符号，地址和一个或多个数据符号的帧，以及 当写入指示符识别写入帧时，驱动器用于驱动与地址相关联的读取数据。 还提出了各种其他方面。 这些方面提供了在单个有线总线上的通信，其允许减少引脚，焊盘或设备之间的块间连接。

公开(公告)号：US06333954B1

公开(公告)日：2001-12-25

申请号：US09422920

申请日：1999-10-21

申请人： David Hansquine

发明人： David Hansquine

IPC分类号： H04L2706

CPC分类号： H03M13/6566 ,  H03M13/395 ,  H03M13/4107 ,  H03M13/4169

摘要： The present invention discloses a system and system of performing an add-compare-select butterfly operation in an implementation of the Viterbi algorithm. The system includes a first memory element for storing a plurality of source state metrics. The first memory element is coupled to a multiplexer which is capable of selecting between a first and second operating path based on even and odd clock cycles. The multiplexer is coupled to an add-compare-select mechanism, which calculates the target state metrics for each of the source state metrics. A second storage element, coupled to the add-compare-select mechanism and the multiplexer, is used to temporarily store the target state metrics while a third storage element stores a predetermined logic bit which corresponds to the lowest value target state metric. The multiplexer therefore selects the first operating path during even clock cycles and supplies the source state metrics from the first memory element to the add-compare-select mechanism to generate target state metrics. During odd clock cycles, the multiplexer selects the second operating path to access the second memory element and use the previously calculated target state metrics as intermediate source state metrics, such that the add-compare-select mechanism generates the target state metrics based on the intermediate source state metrics.

摘要翻译： 本发明公开了一种在维特比算法的实现中执行加法比较选择蝶形运算的系统和系统。 该系统包括用于存储多个源状态度量的第一存储器元件。 第一存储器元件耦合到多路复用器，其能够基于偶数和奇数时钟周期在第一和第二操作路径之间进行选择。 多路复用器耦合到加法比较选择机制，其为每个源状态度量计算目标状态度量。 耦合到加法比较选择机制和多路复用器的第二存储元件用于临时存储目标状态度量，而第三存储元件存储对应于最低值目标状态度量的预定逻辑位。 因此，多路复用器在偶数时钟周期期间选择第一操作路径，并将源状态度量从第一存储器元件提供给加法比较选择机制以产生目标状态度量。 在奇数时钟周期期间，多路复用器选择第二操作路径以访问第二存储器元件，并使用先前计算的目标状态度量作为中间源状态度量，使得加法比较选择机制基于中间级 源状态指标。

公开(公告)号：US06278715B1

公开(公告)日：2001-08-21

申请号：US09187686

申请日：1998-11-05

申请人： David Hansquine

发明人： David Hansquine

IPC分类号： H04L1254

CPC分类号： H03M13/2782 ,  H03M13/2785

摘要： A voice and data communication system and method for receiving symbols for a plurality of channels into chunks included within buffers, each chunk holding symbols for only a corresponding one of the plurality of channels. As complete frames are received and decoded, the chunks holding the symbols, that are decoded, are freed up to be used for reception of newly arriving symbols included in newly arriving frames.

摘要翻译： 一种语音和数据通信系统和方法，用于将多个信道的符号接收到包括在缓冲器内的块，每个块仅保存多个信道中对应的一个信道的符号。 当接收和解码完整的帧时，保存被解码的符号的块被释放以用于接收新到达的帧中包括的新到达的符号。