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    Condition code register architecture for supporting multiple execution units
    1.
    发明授权
    Condition code register architecture for supporting multiple execution units 有权
    用于支持多个执行单元的条件码寄存器架构

    公开(公告)号：US06629235B1

    公开(公告)日：2003-09-30

    申请号：US09564943

    申请日：2000-05-05

    申请人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

    发明人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

    IPC分类号： G06F944

    CPC分类号： G06F9/30094 ,  G06F9/3842

    摘要： A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.

    摘要翻译： 公开了一种用于支持多个执行单元的条件码寄存器架构。 主执行单元耦合主状态代码寄存器，使得由主执行单元生成的条件代码被存储在主状态代码寄存器中。 非主执行单元耦合到阴影条件代码寄存器，使得由非主执行单元生成的条件代码被存储在阴影条件代码寄存器中。 耦合到主执行单元和非主执行单元的标签单元，使得只有在标签单元内的相应条目被引用到主执行单元或主条件代码时才能读取主条件代码寄存器内的条目 寄存器。

    Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions
    2.
    发明授权
    Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions 有权
    加速评估条件设置和分支指令对的处理器和方法

    公开(公告)号：US06598153B1

    公开(公告)日：2003-07-22

    申请号：US09458407

    申请日：1999-12-10

    申请人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

    发明人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

    IPC分类号： G06F938

    CPC分类号： G06F9/30094 ,  G06F9/3842

    摘要： A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.

    摘要翻译： 促进条件分支指令的加速分辨率的处理器包括取指定多个指令的指令定序器和检测器，其在多个取指令中检测条件设置指令和依赖于条件设置的条件转移指令 指令。 处理器还包括解码器，其解码条件分支指令以产生解码条件类型和执行单元。 响应于条件设置指令和条件转移指令的检测，执行单元通过在单个操作中评估条件设置指令和解码条件类型来解析条件转移指令。 由于条件码比特不像现有技术的处理器那样计算或存储为中间结果，所以分支分辨率被加速。

    Memory with combined line and word access
    3.
    发明授权
    Memory with combined line and word access 有权
    内存具有组合的行和字访问

    公开(公告)号：US07617338B2

    公开(公告)日：2009-11-10

    申请号：US11050040

    申请日：2005-02-03

    申请人： Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Osamu Takahashi

    发明人： Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Osamu Takahashi

    IPC分类号： G06F13/28 ,  G06F5/00

    CPC分类号： G06F13/28 ,  G06F13/1626 ,  G06F13/1663

    摘要： A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

    摘要翻译： 提出了一种具有组合线和字访问的存储器的处理器的系统。 系统执行窄读/写存储器访问，并使用多路复用器和锁存器对相同存储体进行宽读/写存储器存取以指导数据。 该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。 在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。 通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

    System and method for tracking messages between a processing unit and an external device
    4.
    发明授权
    System and method for tracking messages between a processing unit and an external device 有权
    用于跟踪处理单元和外部设备之间的消息的系统和方法

    公开(公告)号：US07836222B2

    公开(公告)日：2010-11-16

    申请号：US10606582

    申请日：2003-06-26

    申请人： Michael Norman Day ,  Brian King Flachs ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

    发明人： Michael Norman Day ,  Brian King Flachs ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

    IPC分类号： G06F3/00 ,  G11C8/00

    CPC分类号： H04Q3/545 ,  H04Q2213/13106

    摘要： An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.

    摘要翻译： 使用信道计数器与信道计数读取指令组合的装置作为提供给定信道中的数据有效或先前未被读取的信息的手段。 在信道被定义为阻塞的情况下，计数器还可以用于防止在信道使用的寄存器中无意中覆盖数据，或者替代地，当给定计数时，防止与分配给该信道的设备的进一步通信 发生。 智能外部设备还可以使用发送到计数机构的通道计数读取指令来读取和写入通道。

    Lowered PU power usage method and apparatus
    5.
    发明授权
    Lowered PU power usage method and apparatus 失效
    降低PU功率使用方法和装置

    公开(公告)号：US07197655B2

    公开(公告)日：2007-03-27

    申请号：US10606581

    申请日：2003-06-26

    申请人： Brian King Flachs ,  John Samuel Liberty ,  Harm Peter Hofstee

    发明人： Brian King Flachs ,  John Samuel Liberty ,  Harm Peter Hofstee

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3209

    摘要： Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.

    摘要翻译： 公开了一种根据预定准则将计算机程序指令置于指令通道中的装置，使得至少一些外部事件指令被放置在特殊的“阻塞通道”中。 在通道特定计数器中监视通道中的指令数。 当计算机处理器正在等待来自外部实体事件的响应（换句话说，阻止PU正在尝试的操作），如由阻塞计数器所指示的，处于预定值，整个PU或至少处理器 在等待外部事件响应的情况下，诸如数学逻辑的辅助组件被停用以节省电力，直到接收到等待的外部事件响应。

    Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor
    7.
    发明授权
    Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor 有权
    用于传送数据以维持双端处理器中优选插槽位置的系统和方法

    公开(公告)号：US08145804B2

    公开(公告)日：2012-03-27

    申请号：US12563756

    申请日：2009-09-21

    申请人： Brian King Flachs ,  Brad William Michael ,  Nicolas Maeding ,  Shigeaki Iwasa ,  Seiji Maeda ,  Hiroo Hayashi

    发明人： Brian King Flachs ,  Brad William Michael ,  Nicolas Maeding ,  Shigeaki Iwasa ,  Seiji Maeda ,  Hiroo Hayashi

    IPC分类号： G06F13/28

    CPC分类号： G06F9/30007 ,  G06F9/3824

    摘要： A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.

    摘要翻译： 一种具有多个处理元件的双端式多处理器系统，每个处理单元包括处理器核心，本地存储器和存储器流控制器。 存储器流控制器在本地存储器和处理元件外部的数据源之间传送数据。 如果处理元件和数据源实现具有相同字节数的数据表示，则每个多字数据行以与数据源中相同的字顺序存储在本地存储器中。 如果处理元件和数据源实现具有不同端点的数据表示，则当数据在本地存储器和数据源之间传送时，每个多字数据行的字被转置。 处理元件可以包括用于添加双字的电路，其中，根据数据行中的字是否被转置，电路可以交替地将位从第一个字运送到第二个字，反之亦然。

    Systems and Methods for Transferring Data to Maintain Preferred Slot Positions in a Bi-endian Processor
    8.
    发明申请
    Systems and Methods for Transferring Data to Maintain Preferred Slot Positions in a Bi-endian Processor 有权
    用于传输数据以保持双端处理器中优选插槽位置的系统和方法

    公开(公告)号：US20110072170A1

    公开(公告)日：2011-03-24

    申请号：US12563756

    申请日：2009-09-21

    申请人： Brian King Flachs ,  Brad William Michael ,  Nicolas Maeding ,  Shigeaki Iwasa ,  Seiji Maeda ,  Hiroo Hayashi

    发明人： Brian King Flachs ,  Brad William Michael ,  Nicolas Maeding ,  Shigeaki Iwasa ,  Seiji Maeda ,  Hiroo Hayashi

    IPC分类号： G06F13/28 ,  G06F12/00 ,  G06F12/08

    CPC分类号： G06F9/30007 ,  G06F9/3824

    摘要： A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.

    摘要翻译： 一种具有多个处理元件的双端式多处理器系统，每个处理单元包括处理器核心，本地存储器和存储器流控制器。 存储器流控制器在本地存储器和处理元件外部的数据源之间传送数据。 如果处理元件和数据源实现具有相同字节数的数据表示，则每个多字数据行以与数据源中相同的字顺序存储在本地存储器中。 如果处理元件和数据源实现具有不同端点的数据表示，则当数据在本地存储器和数据源之间传送时，每个多字数据行的字被转置。 处理元件可以包括用于添加双字的电路，其中，根据数据行中的字是否被转置，电路可以交替地将位从第一个字运送到第二个字，反之亦然。