公开(公告)号：US06629235B1

公开(公告)日：2003-09-30

申请号：US09564943

申请日：2000-05-05

申请人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

发明人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

IPC分类号： G06F944

CPC分类号： G06F9/30094 ,  G06F9/3842

摘要： A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.

摘要翻译： 公开了一种用于支持多个执行单元的条件码寄存器架构。 主执行单元耦合主状态代码寄存器，使得由主执行单元生成的条件代码被存储在主状态代码寄存器中。 非主执行单元耦合到阴影条件代码寄存器，使得由非主执行单元生成的条件代码被存储在阴影条件代码寄存器中。 耦合到主执行单元和非主执行单元的标签单元，使得只有在标签单元内的相应条目被引用到主执行单元或主条件代码时才能读取主条件代码寄存器内的条目 寄存器。

公开(公告)号：US06598153B1

公开(公告)日：2003-07-22

申请号：US09458407

申请日：1999-12-10

申请人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

发明人： Brian King Flachs ,  Harm Peter Hofstee ,  Kevin John Nowka

IPC分类号： G06F938

CPC分类号： G06F9/30094 ,  G06F9/3842

摘要： A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.

摘要翻译： 促进条件分支指令的加速分辨率的处理器包括取指定多个指令的指令定序器和检测器，其在多个取指令中检测条件设置指令和依赖于条件设置的条件转移指令 指令。 处理器还包括解码器，其解码条件分支指令以产生解码条件类型和执行单元。 响应于条件设置指令和条件转移指令的检测，执行单元通过在单个操作中评估条件设置指令和解码条件类型来解析条件转移指令。 由于条件码比特不像现有技术的处理器那样计算或存储为中间结果，所以分支分辨率被加速。

公开(公告)号：US07836222B2

公开(公告)日：2010-11-16

申请号：US10606582

申请日：2003-06-26

申请人： Michael Norman Day ,  Brian King Flachs ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

发明人： Michael Norman Day ,  Brian King Flachs ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

IPC分类号： G06F3/00 ,  G11C8/00

CPC分类号： H04Q3/545 ,  H04Q2213/13106

摘要： An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.

摘要翻译： 使用信道计数器与信道计数读取指令组合的装置作为提供给定信道中的数据有效或先前未被读取的信息的手段。 在信道被定义为阻塞的情况下，计数器还可以用于防止在信道使用的寄存器中无意中覆盖数据，或者替代地，当给定计数时，防止与分配给该信道的设备的进一步通信 发生。 智能外部设备还可以使用发送到计数机构的通道计数读取指令来读取和写入通道。

公开(公告)号：US07197655B2

公开(公告)日：2007-03-27

申请号：US10606581

申请日：2003-06-26

申请人： Brian King Flachs ,  John Samuel Liberty ,  Harm Peter Hofstee

发明人： Brian King Flachs ,  John Samuel Liberty ,  Harm Peter Hofstee

IPC分类号： G06F1/00

CPC分类号： G06F1/3209

摘要： Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.

摘要翻译： 公开了一种根据预定准则将计算机程序指令置于指令通道中的装置，使得至少一些外部事件指令被放置在特殊的“阻塞通道”中。 在通道特定计数器中监视通道中的指令数。 当计算机处理器正在等待来自外部实体事件的响应（换句话说，阻止PU正在尝试的操作），如由阻塞计数器所指示的，处于预定值，整个PU或至少处理器 在等待外部事件响应的情况下，诸如数学逻辑的辅助组件被停用以节省电力，直到接收到等待的外部事件响应。

公开(公告)号：US06600959B1

公开(公告)日：2003-07-29

申请号：US09498934

申请日：2000-02-04

申请人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi

发明人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi

IPC分类号： G05B1918

CPC分类号： H03K17/693 ,  H03K5/06

摘要： A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.

摘要翻译： 在微处理器控制逻辑中使用动态可编程逻辑阵列的方法和装置通过专门用于控制逻辑的可编程逻辑阵列来为数据处理系统提供降低的功率和增加的时钟频率。 该方法和装置通过在微处理器内提供控制逻辑评估和数据传输的重叠来进一步简化控制逻辑的设计和微处理器内的定时闭合。

公开(公告)号：US07617338B2

公开(公告)日：2009-11-10

申请号：US11050040

申请日：2005-02-03

申请人： Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Osamu Takahashi

IPC分类号： G06F13/28 ,  G06F5/00

CPC分类号： G06F13/28 ,  G06F13/1626 ,  G06F13/1663

摘要： A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

摘要翻译： 提出了一种具有组合线和字访问的存储器的处理器的系统。 系统执行窄读/写存储器访问，并使用多路复用器和锁存器对相同存储体进行宽读/写存储器存取以指导数据。 该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。 在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。 通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

公开(公告)号：US06836849B2

公开(公告)日：2004-12-28

申请号：US09826986

申请日：2001-04-05

申请人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

发明人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

IPC分类号： G06F126

CPC分类号： G06F1/3203

摘要： A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system. Then controller generates controls and applies them to individual processors to achieve the performance goals.

摘要翻译： 描述了一种用于管理多处理器（MP）系统的功率和性能的方法和控制器。 控制器接收与MP系统内的物理参数对应的传感器数据。 控制器还接收与MP系统对应的服务质量和策略参数。 服务质量参数定义了对客户使用MP系统的承诺。 策略参数对应于MP系统的输入和输出的操作限制。 操作输入限制涉及功率或单个处理器可用性的成本和可用性。 操作输出限制涉及允许MP系统中的个体或一组处理器在特定环境中生成的热量，声学噪声水平，EMC等级等。 控制器接收物理参数，服务质量参数和策略参数，并确定MP系统中的MP系统和处理器的性能目标。 然后控制器生成控件并将其应用于各个处理器以实现性能目标。

公开(公告)号：US06212619B1

公开(公告)日：2001-04-03

申请号：US09075918

申请日：1998-05-11

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin John Nowka ,  Joel Abraham Silberman

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin John Nowka ,  Joel Abraham Silberman

IPC分类号： G06F1500

CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A superscalar computer architecture for executing instructions out-of-order, comprising a multiplicity of execution units, a plurality of registers, and a register renaming circuit which generates a list of tags corresponding to specific registers that are not in use during loading of a given instruction. A table is constructed having one bit for each register per instruction in flight. The entries in the table may be combined in a logical OR fashion to create a vector that identifies which registers are in use by instructions that are in flight. Validity bits can also be generated to indicate validity of the generated tags, wherein a generated tag is invalid only if an insufficient number of registers are available during loading of the given instruction. The execution units are preferably pipelined.

摘要翻译： 一种用于执行无序指令的超标量计算机体系结构，包括多个执行单元，多个寄存器和寄存器重命名电路，该电路生成与给定的加载期间不使用的特定寄存器相对应的标签列表 指令。 在飞行中每个指令的每个寄存器构造一个表。 表中的条目可以以逻辑或或者方式组合，以创建一个向量，用于识别正在飞行中的指令使用哪些寄存器。 也可以生成有效位以指示生成的标签的有效性，其中仅当在给定指令的加载期间没有足够数量的寄存器可用时，所生成的标签才是无效的。 执行单元优选地被流水线化。

公开(公告)号：US6014763A

公开(公告)日：2000-01-11

申请号：US7670

申请日：1998-01-15

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin John Nowka ,  Joel Abraham Silberman

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin John Nowka ,  Joel Abraham Silberman

IPC分类号： G01R31/28

CPC分类号： G01R31/318572

摘要： A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.

摘要翻译： 通过将并行扫描输入（扫描数据和扫描控制）转换为串行扫描来扫描集成电路的方法，将串行扫描输入通过扫描电路传送以创建串行扫描输出，将扫描输出从串行转换为并行转换， 从集成电路并行扫描输出到测试仪。 通过将测试仪与集成电路的分频时钟信号（1 / N）同步，得到测试仪时钟信号。 通信以测试仪时钟信号的速度进行，但扫描以被测设备的全部操作速度运行。 对于超过1 GHz的速度，可以实现高速扫描测试。

公开(公告)号：US06335650B1

公开(公告)日：2002-01-01

申请号：US09670829

申请日：2000-09-28

申请人： David William Boerstler ,  Harm Peter Hofstee ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： David William Boerstler ,  Harm Peter Hofstee ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： H03H1126

CPC分类号： H03K5/133 ,  H03K19/00384 ,  H03K19/018585 ,  H03K2005/0013

摘要： A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.

摘要翻译： 公开了一种用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置。 电压电平检测器和延迟装置耦合到能够在多个电源电压下工作的集成电路的关键定时电路。 电压电平检测器检测集成电路正在工作的电源电压。 当集成电路的工作电源电压从第一电压电平变化到第二电压电平时，电压电平检测器向延迟装置和当前增强电路发送信号，使得延迟装置和电流增强电路可以自动修改 来自关键定时电路的输出信号的切换时间的延迟。