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    Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin
    5.
    发明授权
    Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin 有权
    通过结合部分金属翅片来减少多栅极器件的外部电阻

    公开(公告)号：US07763943B2

    公开(公告)日：2010-07-27

    申请号：US11964623

    申请日：2007-12-26

    申请人： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    发明人： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

    摘要翻译： 通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。 在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域 设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体 部分联接在一起。

    Reducing external resistance of a multi-gate device using spacer processing techniques
    6.
    发明授权
    Reducing external resistance of a multi-gate device using spacer processing techniques 有权
    使用间隔物处理技术降低多栅极器件的外部电阻

    公开(公告)号：US08030163B2

    公开(公告)日：2011-10-04

    申请号：US11964593

    申请日：2007-12-26

    申请人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

    发明人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/785

    摘要： A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A dielectric film is formed that is coupled to the source and drain regions. The sacrificial gate electrode is removed and a spacer gate dielectric is deposited to the gate region wherein substantially no spacer gate dielectric is deposited to the source and drain regions. The spacer gate dielectric is etched to completely remove the spacer gate dielectric from the gate region area that is to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric that is to be coupled with the final gate electrode that remains coupled with the dielectric film.

    摘要翻译： 一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上。 牺牲栅电极被图案化，使得它被耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到源极和漏极区域。 形成了与源极和漏极区域耦合的电介质膜。 牺牲栅极电极被去除，并且间隔栅极电介质沉积到栅极区域，其中基本上没有间隔栅极电介质沉积到源区和漏极区。 蚀刻间隔栅极电介质以完全去除要与最终栅电极耦合的栅极区域的间隔栅极电介质，除了与最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外， 保持与电介质膜耦合。

    Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application
    7.
    发明申请
    Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application 审中-公开
    集成电路，含有1T-1C的嵌入式存储单元以及用于嵌入式存储器应用的1T-1C存储单元的制造方法

    公开(公告)号：US20100155801A1

    公开(公告)日：2010-06-24

    申请号：US12317507

    申请日：2008-12-22

    申请人： Brian S. Doyle ,  Dinesh Somasekhar ,  Gilbert Dewey ,  Satyarth Suri

    发明人： Brian S. Doyle ,  Dinesh Somasekhar ,  Gilbert Dewey ,  Satyarth Suri

    IPC分类号： H01L29/94 ,  H01L29/06 ,  H01L21/8242

    CPC分类号： H01L28/90 ,  H01L27/10894 ,  H01L27/10897

    摘要： An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of the capacitor. In the same or another embodiment, the integrated circuit may act as a 1T-1C embedded memory cell including the semiconducting substrate, an electrically insulating stack (160) over the semiconducting substrate, a transistor (140) including a source/drain region (142) within the semiconducting substrate and a gate region (141) above the semiconducting substrate, a trench (111) extending through the electrically insulating layers and into the semiconducting substrate, a first electrically insulating layer (131) located within the trench, and the capacitor located within the trench interior to the first electrically insulating layer.

    摘要翻译： 集成电路包括半导体衬底（110），半导体衬底上的导电层（120）和至少部分地嵌入在半导体衬底内的电容器（130），使得电容器完全在导电层的下面。 存储节点电压位于电容器的外层（132）上。 在相同或另一个实施例中，集成电路可以用作包括半导体衬底的1T-1C嵌入式存储单元，半导体衬底上的电绝缘堆叠（160），包括源极/漏极区域（142）的晶体管（140） ）和在半导体衬底上方的栅极区（141），延伸穿过电绝缘层并进入半导体衬底的沟槽（111），位于沟槽内的第一电绝缘层（131）和电容器 位于第一电绝缘层的沟槽内部。

    REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES
    9.
    发明申请
    REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES 审中-公开
    使用间隔加工技术降低多门装置的外部电阻

    公开(公告)号：US20110284965A1

    公开(公告)日：2011-11-24

    申请号：US13204987

    申请日：2011-08-08

    申请人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

    发明人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/785

    摘要： Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

    摘要翻译： 通常描述使用间隔物处理技术降低多栅极器件的外部电阻。 在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在 源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质 将一个或多个多栅极翅片的源极和漏极区域耦合到所述一个或多个多栅极散热片的栅极区域;将所述牺牲栅极电极从所述一个或多个至多个栅极鳍片的栅极区域移除;将间隔栅极电介质沉积到所述一个或多个栅极栅极栅极区域; 更多的多栅极鳍片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质保护 膜和蚀刻间隔栅极电介质以从栅极区域区域完全去除间隔栅极电介质，以与最终栅极电极耦合，除了与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外 与电介质膜。

    Unity beta ratio tri-gate transistor static random access memory (SRAM)
    10.
    发明授权
    Unity beta ratio tri-gate transistor static random access memory (SRAM) 有权
    统一beta比三栅晶体管静态随机存取存储器（SRAM）

    公开(公告)号：US07825437B2

    公开(公告)日：2010-11-02

    申请号：US12006082

    申请日：2007-12-28

    申请人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

    发明人： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

    IPC分类号： H01L27/118

    CPC分类号： H01L27/1104 ,  H01L27/11

    摘要： In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.

    摘要翻译： 通常，在一个方面，一种方法包括在半导体衬底中形成N-扩散和P-扩散翅片。 在半导体衬底上形成P扩散栅极层，并从N扩散鳍片上去除。 在半导体衬底上形成通过栅极的N扩散栅极层，并从P扩散鳍片和下拉的N扩散鳍片中去除。 在半导体衬底上形成下拉式N扩散层。