公开(公告)号：US20060009931A1

公开(公告)日：2006-01-12

申请号：US11224277

申请日：2005-09-12

申请人： Brian Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

发明人： Brian Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

IPC分类号： G01R31/00

CPC分类号： G06F11/24 ,  H02H1/00 ,  H02H3/385 ,  H02H7/267

摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

公开(公告)号：US06944692B2

公开(公告)日：2005-09-13

申请号：US09951928

申请日：2001-09-13

申请人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

发明人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

IPC分类号： H04L25/02 ,  G06F1/10 ,  G06F11/24 ,  G06F13/00 ,  G06F13/42 ,  G06K5/04 ,  H02H1/00 ,  H02H3/38 ,  H02H7/26 ,  H04L25/03 ,  G06F11/04

CPC分类号： G06F11/24 ,  H02H1/00 ,  H02H3/385 ,  H02H7/267

摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

摘要翻译： 提供了一种用于通过多变量眼窗自动校准I / O的方法和装置。 发射机可以通过多条信号线对集成电路（IC）的接收机进行数据传输。 可以根据某些参数或参数集进行数据传输。 参数可以包括传输信号的电压电平或定时延迟。 接收机可以确定是否在每个信号线上接收到正确的数据值。 结果可以记录在与接收器相同的IC中的存储机构中。 对于每个信号线，存储机构可以存储对应于用于数据传输的特定参数的通过/失败结果。 系统可以从存储机构中选择要在多条信号线中的每条信号上进行后续传输的参数。

公开(公告)号：US07296104B2

公开(公告)日：2007-11-13

申请号：US11224277

申请日：2005-09-12

申请人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

发明人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

IPC分类号： G06F13/42 ,  G06F11/04 ,  G06K5/04

CPC分类号： G06F11/24 ,  H02H1/00 ,  H02H3/385 ,  H02H7/267

摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

摘要翻译： 提供了一种用于通过多变量眼窗自动校准I / O的方法和装置。 发射机可以通过多条信号线对集成电路（IC）的接收机进行数据传输。 可以根据某些参数或参数集进行数据传输。 参数可以包括传输信号的电压电平或定时延迟。 接收机可以确定是否在每个信号线上接收到正确的数据值。 结果可以记录在与接收器相同的IC中的存储机构中。 对于每个信号线，存储机构可以存储对应于用于数据传输的特定参数的通过/失败结果。 系统可以从存储机构中选择要在多条信号线中的每条信号上进行后续传输的参数。

公开(公告)号：US06937680B2

公开(公告)日：2005-08-30

申请号：US09842332

申请日：2001-04-24

申请人： Wai Fong ,  Jyh-Ming Jong ,  Leo Yuan ,  Brian Smith ,  Prabhansu Chakrabarti

发明人： Wai Fong ,  Jyh-Ming Jong ,  Leo Yuan ,  Brian Smith ,  Prabhansu Chakrabarti

IPC分类号： G06F1/12 ,  H03L7/081 ,  H03L7/095 ,  H04L7/00

CPC分类号： H03L7/0812 ,  H03L7/095 ,  H04L7/0008

摘要： A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal. The resetting of the source synchronous receiver may be performed locally, and does not reset the core logic of the device in which it is implemented, nor any other source synchronous port on the device. Thus, other source synchronous ports on the device, as well as the core logic, may be able to continue operations as normal. The method and apparatus may include a source synchronous receiver that is hot-swappable.

摘要翻译： 一种用于操作源同步接收机的方法和装置。 在一个实施例中，源同步接收器可以包括包括时钟检测器和时钟信号缓冲器的时钟接收器。 时钟检测器可以被配置为响应于检测到第一时钟信号而检测第一时钟信号并且断言时钟检测信号。 时钟缓冲器可以接收第一时钟信号并产生可以被驱动到数字锁相环（DLL）电路的第二时钟信号，其中第二时钟信号被再生并被驱动到源同步接收器的数据缓冲器。 时钟检测信号可以由时钟验证电路接收。 时钟验证电路可以被配置为在接收到时钟检测信号的失败时发起源同步接收器的复位。 源同步接收机的复位可以在本地执行，并且不重置其实现的设备的核心逻辑，也不会重置设备上的任何其他源同步端口。 因此，设备上的其他源同步端口以及核心逻辑可能能够正常地继续操作。 该方法和装置可以包括热插拔的源同步接收器。

公开(公告)号：US06880118B2

公开(公告)日：2005-04-12

申请号：US09999877

申请日：2001-10-25

申请人： Cecilia T. Chen ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Brian L. Smith

发明人： Cecilia T. Chen ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Brian L. Smith

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/31858 ,  G01R31/318544

摘要： A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.

摘要翻译： 源同步测试方法和设备。 在一个实施例中，配置用于源同步I / O事务的集成电路（IC）可以是被测设备（DUT），并且可以被安装到负载板以进行测试。 负载板可以电耦合到测试系统。 测试系统可以将第一测试数据转移到负载板上的第一个IC中。 然后，第一芯片可以通过源同步线或具有多条线的源同步链路将第一测试数据发送到第二IC。 然后响应于源同步传输产生的第二测试数据从第二IC转移到测试器。 然后分析第二个测试数据。 分析可以包括将第二数据与预期数据进行比较，和/或还可以包括分析关于眼睛窗口的第二数据。

公开(公告)号：US06404839B1

公开(公告)日：2002-06-11

申请号：US09797033

申请日：2001-02-28

申请人： Wai Fong ,  Jyh-Ming Jong

发明人： Wai Fong ,  Jyh-Ming Jong

IPC分类号： H03K2100

CPC分类号： H03K23/505 ,  H03K21/10

摘要： A clock divider circuit having a fifty per cent duty cycle and multiple integer ratios for dividing an input clock signal. In one embodiment, a clock divider circuit may include a chain of serially-coupled flip-flops. The chain may include at least a first and a second flip-flop, both of which may be triggered by a first edge of an input clock signal. A third flip-flop, coupled to (but not part of) the chain may be configured to be triggered by a second edge of the input clock signal. The third flip-flop may be coupled to an output circuit. In addition to receiving the output signal from the third flip-flop, the output circuit may also receive signals from the chain of serially-coupled flip-flops. The output circuit may drive a second clock signal, which may be produced by dividing the first clock signal based upon the signals it receives. The first clock signal may be divided by an even or an odd integer ratio, or may be divided by an integer ratio (e.g. 2.5), although clock signals produced based on a decimal ratio may have a duty cycle that is not fifty per cent.

摘要翻译： 一个时钟分频电路，具有五十％的占空比和多个整数比来分频输入时钟信号。 在一个实施例中，时钟分频器电路可以包括串联的触发器链。 该链可以包括至少第一和第二触发器，它们都可以由输入时钟信号的第一边缘触发。 耦合到（但不是部分）链的第三触发器可以被配置为由输入时钟信号的第二边缘触发。 第三触发器可以耦合到输出电路。 除了从第三触发器接收输出信号之外，输出电路还可以从串联耦合的触发器链接收信号。 输出电路可以驱动第二时钟信号，其可以通过基于其接收的信号划分第一时钟信号来产生。 第一时钟信号可以除以偶或奇整数比，或者可以除以整数比（例如2.5），尽管基于小数比率产生的时钟信号可以具有不为百分之五十的占空比。