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    Automated calibration of I/O over a multi-variable eye window
    1.
    发明申请
    Automated calibration of I/O over a multi-variable eye window 有权

    公开(公告)号：US20060009931A1

    公开(公告)日：2006-01-12

    申请号：US11224277

    申请日：2005-09-12

    申请人： Brian Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

    发明人： Brian Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

    IPC分类号： G01R31/00

    CPC分类号： G06F11/24 ,  H02H1/00 ,  H02H3/385 ,  H02H7/267

    摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

    Automated calibration of I/O over a multi-variable eye window
    2.
    发明授权
    Automated calibration of I/O over a multi-variable eye window 有权
    通过多变量眼睛窗口自动校准I / O

    公开(公告)号：US06944692B2

    公开(公告)日：2005-09-13

    申请号：US09951928

    申请日：2001-09-13

    申请人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

    发明人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

    IPC分类号： H04L25/02 ,  G06F1/10 ,  G06F11/24 ,  G06F13/00 ,  G06F13/42 ,  G06K5/04 ,  H02H1/00 ,  H02H3/38 ,  H02H7/26 ,  H04L25/03 ,  G06F11/04

    CPC分类号： G06F11/24 ,  H02H1/00 ,  H02H3/385 ,  H02H7/267

    摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

    摘要翻译： 提供了一种用于通过多变量眼窗自动校准I / O的方法和装置。 发射机可以通过多条信号线对集成电路（IC）的接收机进行数据传输。 可以根据某些参数或参数集进行数据传输。 参数可以包括传输信号的电压电平或定时延迟。 接收机可以确定是否在每个信号线上接收到正确的数据值。 结果可以记录在与接收器相同的IC中的存储机构中。 对于每个信号线，存储机构可以存储对应于用于数据传输的特定参数的通过/失败结果。 系统可以从存储机构中选择要在多条信号线中的每条信号上进行后续传输的参数。

    Automated calibration of I/O over a multi-variable eye window
    3.
    发明授权
    Automated calibration of I/O over a multi-variable eye window 有权
    通过多变量眼睛窗口自动校准I / O

    公开(公告)号：US07296104B2

    公开(公告)日：2007-11-13

    申请号：US11224277

    申请日：2005-09-12

    申请人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

    发明人： Brian L. Smith ,  Jue Wu ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Prabhansu Chakrabarti

    IPC分类号： G06F13/42 ,  G06F11/04 ,  G06K5/04

    CPC分类号： G06F11/24 ,  H02H1/00 ,  H02H3/385 ,  H02H7/267

    摘要： A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

    摘要翻译： 提供了一种用于通过多变量眼窗自动校准I / O的方法和装置。 发射机可以通过多条信号线对集成电路（IC）的接收机进行数据传输。 可以根据某些参数或参数集进行数据传输。 参数可以包括传输信号的电压电平或定时延迟。 接收机可以确定是否在每个信号线上接收到正确的数据值。 结果可以记录在与接收器相同的IC中的存储机构中。 对于每个信号线，存储机构可以存储对应于用于数据传输的特定参数的通过/失败结果。 系统可以从存储机构中选择要在多条信号线中的每条信号上进行后续传输的参数。

    Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection
    4.
    发明授权
    Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection 有权
    源同步接收器链路初始化和输入浮点控制通过时钟检测和DLL锁定检测

    公开(公告)号：US06937680B2

    公开(公告)日：2005-08-30

    申请号：US09842332

    申请日：2001-04-24

    申请人： Wai Fong ,  Jyh-Ming Jong ,  Leo Yuan ,  Brian Smith ,  Prabhansu Chakrabarti

    发明人： Wai Fong ,  Jyh-Ming Jong ,  Leo Yuan ,  Brian Smith ,  Prabhansu Chakrabarti

    IPC分类号： G06F1/12 ,  H03L7/081 ,  H03L7/095 ,  H04L7/00

    CPC分类号： H03L7/0812 ,  H03L7/095 ,  H04L7/0008

    摘要： A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal. The resetting of the source synchronous receiver may be performed locally, and does not reset the core logic of the device in which it is implemented, nor any other source synchronous port on the device. Thus, other source synchronous ports on the device, as well as the core logic, may be able to continue operations as normal. The method and apparatus may include a source synchronous receiver that is hot-swappable.

    摘要翻译： 一种用于操作源同步接收机的方法和装置。 在一个实施例中，源同步接收器可以包括包括时钟检测器和时钟信号缓冲器的时钟接收器。 时钟检测器可以被配置为响应于检测到第一时钟信号而检测第一时钟信号并且断言时钟检测信号。 时钟缓冲器可以接收第一时钟信号并产生可以被驱动到数字锁相环（DLL）电路的第二时钟信号，其中第二时钟信号被再生并被驱动到源同步接收器的数据缓冲器。 时钟检测信号可以由时钟验证电路接收。 时钟验证电路可以被配置为在接收到时钟检测信号的失败时发起源同步接收器的复位。 源同步接收机的复位可以在本地执行，并且不重置其实现的设备的核心逻辑，也不会重置设备上的任何其他源同步端口。 因此，设备上的其他源同步端口以及核心逻辑可能能够正常地继续操作。 该方法和装置可以包括热插拔的源同步接收器。

    Method and circuitry for a pre-emphasis scheme for single-ended center taped terminated high speed digital signaling
    5.
    发明授权
    Method and circuitry for a pre-emphasis scheme for single-ended center taped terminated high speed digital signaling 有权
    用于单端中心录音终端高速数字信号的预加重方案的方法和电路

    公开(公告)号：US06518792B2

    公开(公告)日：2003-02-11

    申请号：US09879501

    申请日：2001-06-11

    申请人： Jyh-Ming Jong ,  Prabhansu Chakrabarti ,  Leo Yuan

    发明人： Jyh-Ming Jong ,  Prabhansu Chakrabarti ,  Leo Yuan

    IPC分类号： H03K190175

    CPC分类号： H04L25/0286 ,  H04L25/0272

    摘要： A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized. If the next logic signal has a logic value that is equivalent to either the first logic signal or the second logic signal, it may be transmitted without pre-emphasis.

    摘要翻译： 一种预先强调传输逻辑信号的方法和电路。 该方法和电路可以应用于单端中心点终端I / O线。 在一个实施例中，驱动器电路可以被配置为监视由驱动器电路发送的信号的逻辑值（即逻辑0，逻辑1或逻辑低，逻辑高）。 驱动器电路可以将要发送的下一逻辑信号的逻辑值与先前发送的第一信号和第二先前发送的信号进行比较。 基于要发送的下一逻辑信号的逻辑值以及第一和第二逻辑信号的逻辑值，可能发生下一个逻辑信号的预加重。 如果第一和第二逻辑信号具有相同的逻辑值，并且下一逻辑信号具有不同的值，则可以预先强调下一个逻辑值。 如果下一个逻辑信号具有等同于第一逻辑信号或第二逻辑信号的逻辑值，则可以在没有预加重的情况下发送它。

    Method and apparatus for detecting valid clock signals at a clock receiver circuit
    6.
    发明授权
    Method and apparatus for detecting valid clock signals at a clock receiver circuit 有权
    用于在时钟接收机电路检测有效时钟信号的方法和装置

    公开(公告)号：US06737892B2

    公开(公告)日：2004-05-18

    申请号：US09741485

    申请日：2000-12-18

    申请人： Jyh-Ming Jong ,  Chung-Hsiao Wu ,  Prabhansu Chakrabarti ,  Leo Yuan

    发明人： Jyh-Ming Jong ,  Chung-Hsiao Wu ,  Prabhansu Chakrabarti ,  Leo Yuan

    IPC分类号： H03K519

    CPC分类号： G06F1/04

    摘要： One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. The system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Next, the system uses the voltage-controlled variable resistor to control a first current. A current mirror is then employed to create a second current from the first current. This second current passes through a resistor to produce a control voltage, which is amplified to produce a validity signal indicating whether or not the clock signal is valid. In one embodiment of the present invention, the system additionally uses at least one capacitor to filter out periodic fluctuations in the validity signal.

    摘要翻译： 本发明的一个实施例提供一种用于在时钟接收器处检测有效时钟信号的系统。 该系统通过在时钟接收器处接收时钟信号并将时钟信号引导到压控可变电阻器的控制输入中来操作。 接下来，系统使用压控可变电阻来控制第一电流。 然后使用电流镜来从第一电流产生第二电流。 该第二电流通过电阻器以产生控制电压，其被放大以产生指示时钟信号是否有效的有效信号。 在本发明的一个实施例中，该系统另外使用至少一个电容器来滤除有效信号中的周期性波动。

    System and method for testing operational transmissions of an integrated circuit
    8.
    发明授权
    System and method for testing operational transmissions of an integrated circuit 有权
    用于测试集成电路的运行传输的系统和方法

    公开(公告)号：US06880118B2

    公开(公告)日：2005-04-12

    申请号：US09999877

    申请日：2001-10-25

    申请人： Cecilia T. Chen ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Brian L. Smith

    发明人： Cecilia T. Chen ,  Jyh-Ming Jong ,  Wai Fong ,  Leo Yuan ,  Brian L. Smith

    IPC分类号： G01R31/3185 ,  G01R31/28

    CPC分类号： G01R31/31858 ,  G01R31/318544

    摘要： A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.

    摘要翻译： 源同步测试方法和设备。 在一个实施例中，配置用于源同步I / O事务的集成电路（IC）可以是被测设备（DUT），并且可以被安装到负载板以进行测试。 负载板可以电耦合到测试系统。 测试系统可以将第一测试数据转移到负载板上的第一个IC中。 然后，第一芯片可以通过源同步线或具有多条线的源同步链路将第一测试数据发送到第二IC。 然后响应于源同步传输产生的第二测试数据从第二IC转移到测试器。 然后分析第二个测试数据。 分析可以包括将第二数据与预期数据进行比较，和/或还可以包括分析关于眼睛窗口的第二数据。

    Selectable clock divider circuit with a 50% duty cycle clock
    9.
    发明授权
    Selectable clock divider circuit with a 50% duty cycle clock 有权
    具有50％占空比时钟的可选择的时钟分频器电路

    公开(公告)号：US06404839B1

    公开(公告)日：2002-06-11

    申请号：US09797033

    申请日：2001-02-28

    申请人： Wai Fong ,  Jyh-Ming Jong

    发明人： Wai Fong ,  Jyh-Ming Jong

    IPC分类号： H03K2100

    CPC分类号： H03K23/505 ,  H03K21/10

    摘要： A clock divider circuit having a fifty per cent duty cycle and multiple integer ratios for dividing an input clock signal. In one embodiment, a clock divider circuit may include a chain of serially-coupled flip-flops. The chain may include at least a first and a second flip-flop, both of which may be triggered by a first edge of an input clock signal. A third flip-flop, coupled to (but not part of) the chain may be configured to be triggered by a second edge of the input clock signal. The third flip-flop may be coupled to an output circuit. In addition to receiving the output signal from the third flip-flop, the output circuit may also receive signals from the chain of serially-coupled flip-flops. The output circuit may drive a second clock signal, which may be produced by dividing the first clock signal based upon the signals it receives. The first clock signal may be divided by an even or an odd integer ratio, or may be divided by an integer ratio (e.g. 2.5), although clock signals produced based on a decimal ratio may have a duty cycle that is not fifty per cent.

    摘要翻译： 一个时钟分频电路，具有五十％的占空比和多个整数比来分频输入时钟信号。 在一个实施例中，时钟分频器电路可以包括串联的触发器链。 该链可以包括至少第一和第二触发器，它们都可以由输入时钟信号的第一边缘触发。 耦合到（但不是部分）链的第三触发器可以被配置为由输入时钟信号的第二边缘触发。 第三触发器可以耦合到输出电路。 除了从第三触发器接收输出信号之外，输出电路还可以从串联耦合的触发器链接收信号。 输出电路可以驱动第二时钟信号，其可以通过基于其接收的信号划分第一时钟信号来产生。 第一时钟信号可以除以偶或奇整数比，或者可以除以整数比（例如2.5），尽管基于小数比率产生的时钟信号可以具有不为百分之五十的占空比。

    Noise margin self-diagnostic receiver logic
    10.
    发明授权
    Noise margin self-diagnostic receiver logic 有权
    噪声余量自诊断接收器逻辑

    公开(公告)号：US07130340B1

    公开(公告)日：2006-10-31

    申请号：US09698622

    申请日：2000-10-27

    申请人： Jyh-Ming Jong ,  Leo Yuan

    发明人： Jyh-Ming Jong ,  Leo Yuan

    IPC分类号： H04B3/46

    CPC分类号： H04B3/46 ,  H04L25/08

    摘要： A noise margin self-diagnostic receiver circuit has been developed. The self-diagnostic circuit includes one comparator for comparing the signal voltage to a high reference voltage, a second comparator for comparing the signal voltage to a low reference voltage, and a logic circuit that activates an alarm if a noise error is detected. The circuit analyzes the data from the comparators and determines if a noise error has occurred dependent on being clocked by one or both of an output from the comparator comparing the signal voltage to the high reference voltage and an output from the comparator comparing the signal voltage to the low reference voltage.

    摘要翻译： 已经开发了噪声容限自诊断接收机电路。 自诊断电路包括用于将信号电压与高参考电压进行比较的一个比较器，用于将信号电压与低参考电压进行比较的第二比较器以及如果检测到噪声误差则激活报警的逻辑电路。 电路分析来自比较器的数据，并且确定是否发生了噪声误差，这取决于由比较器中的一个或两个比较信号电压与高参考电压的时钟，以及来自比较器的输出比较信号电压与 低参考电压。