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    Low power circuit structure with metal gate and high-k dielectric
    5.
    发明授权
    Low power circuit structure with metal gate and high-k dielectric 失效
    具有金属栅极和高k电介质的低功率电路结构

    公开(公告)号：US07807525B2

    公开(公告)日：2010-10-05

    申请号：US12538186

    申请日：2009-08-10

    申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L29/49 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785

    摘要： FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.

    摘要翻译： 公开了具有高k介质栅极绝缘体，含金属栅极和阈值调节盖层的PFET和NFET器件的FET器件结构。 NFET栅极堆叠和PFET栅极堆叠各自具有在NFET器件和PFET器件中相同的部分。 该相同部分至少包含栅极金属层和盖层。 由于相同的部分，器件制造被简化，需要减少数量的掩模。 此外，由于使用单层金属作为两种器件的栅极的结果，NFET和PFET的端子电极可以直接物理接触地彼此对接。 通过高k电介质的氧气曝光进一步调节器件阈值。 阈值是针对低功耗设备操作的。

    Simple Low Power Circuit Structure with Metal Gate and High-k Dielectric
    7.
    发明申请
    Simple Low Power Circuit Structure with Metal Gate and High-k Dielectric 有权
    具有金属栅极和高k介质的简单低功耗电路结构

    公开(公告)号：US20090039434A1

    公开(公告)日：2009-02-12

    申请号：US11835310

    申请日：2007-08-07

    申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

    摘要： FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. Due to the single common metal, device fabrication is simplified, requiring a reduced number of masks. Also, as a further consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. Device thresholds are adjusted by the choice of the common metal material and oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.

    摘要翻译： 公开了具有高k介质栅极绝缘体和含金属栅极的PFET和NFET器件的FET器件结构。 NFET和PFET器件中的栅极的金属层已经由单个公共金属层制造。 由于单个普通金属，器件制造简化，需要减少数量的掩模。 此外，作为使用单层金属作为两种类型的器件的栅极的进一步的结果，NFET和PFET的端子电极可以直接物理接触地彼此对接。 通过选择普通金属材料和高k电介质的氧气曝光来调节器件阈值。 阈值是针对低功耗设备操作的。

    Threshold adjustment for high-K gate dielectric CMOS
    8.
    发明授权
    Threshold adjustment for high-K gate dielectric CMOS 有权
    高K栅极电介质CMOS的阈值调整

    公开(公告)号：US08187961B2

    公开(公告)日：2012-05-29

    申请号：US12535554

    申请日：2009-08-04

    申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/823864 ,  H01L21/28176 ,  H01L27/092 ,  H01L29/6656 ,  Y10S438/981

    摘要： A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.

    摘要翻译： 公开了一种CMOS结构，其中第一类型FET具有极薄的氧化物衬垫。 该薄衬套能够防止氧气到达第一类型FET的高k电介质栅极绝缘体。 CMOS结构的第二种FET器件具有较厚的氧化物衬垫。 结果，氧暴露能够移动第二类型FET的阈值电压，而不影响第一类型FET的阈值。 本公开还教导了用于制造CMOS结构的方法，其中不同类型的FET器件具有不同的厚度衬垫，并且不同类型的FET器件的阈值彼此独立地设置。

    Threshold Adjustment for High-K Gate Dielectric CMOS
    9.
    发明申请
    Threshold Adjustment for High-K Gate Dielectric CMOS 审中-公开
    高K栅介质CMOS的阈值调整

    公开(公告)号：US20080272437A1

    公开(公告)日：2008-11-06

    申请号：US11743101

    申请日：2007-05-01

    申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L27/092 ,  H01L21/3205

    CPC分类号： H01L21/823864 ,  H01L21/28176 ,  H01L27/092 ,  H01L29/6656 ,  Y10S438/981

    摘要： A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.

    摘要翻译： 公开了一种CMOS结构，其中第一类型FET具有极薄的氧化物衬垫。 该薄衬套能够防止氧气到达第一类型FET的高k电介质栅极绝缘体。 CMOS结构的第二种FET器件具有较厚的氧化物衬垫。 结果，氧暴露能够移动第二类型FET的阈值电压，而不影响第一类型FET的阈值。 本公开还教导了用于制造CMOS结构的方法，其中不同类型的FET器件具有不同的厚度衬垫，并且不同类型的FET器件的阈值彼此独立地设置。

    Threshold Adjustment for High-K Gate Dielectric CMOS
    10.
    发明申请
    Threshold Adjustment for High-K Gate Dielectric CMOS 有权
    高K栅介质CMOS的阈值调整

    公开(公告)号：US20090291553A1

    公开(公告)日：2009-11-26

    申请号：US12535554

    申请日：2009-08-04

    申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823864 ,  H01L21/28176 ,  H01L27/092 ,  H01L29/6656 ,  Y10S438/981

    摘要： A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.

    摘要翻译： 公开了一种CMOS结构，其中第一类型FET具有极薄的氧化物衬垫。 该薄衬套能够防止氧气到达第一类型FET的高k电介质栅极绝缘体。 CMOS结构的第二种FET器件具有较厚的氧化物衬垫。 结果，氧暴露能够移动第二类型FET的阈值电压，而不影响第一类型FET的阈值。 本公开还教导了用于制造CMOS结构的方法，其中不同类型的FET器件具有不同的厚度衬垫，并且不同类型的FET器件的阈值彼此独立地设置。