公开(公告)号：US5862005A

公开(公告)日：1999-01-19

申请号：US724977

申请日：1996-10-03

申请人： Michael D. Leis ,  Ara Patapoutian ,  Mathew P. Vea ,  Richard M. Ehrlich ,  Kevin D. Fisher ,  James A. Henson ,  William R. Akin, Jr.

发明人： Michael D. Leis ,  Ara Patapoutian ,  Mathew P. Vea ,  Richard M. Ehrlich ,  Kevin D. Fisher ,  James A. Henson ,  William R. Akin, Jr.

IPC分类号： G11B20/14 ,  G11B5/55 ,  G11B5/596 ,  G11B20/10 ,  G11B20/18 ,  G11B21/08 ,  G11B21/10 ,  G11B27/30 ,  H03M13/23 ,  H04L25/49 ,  G11B5/02 ,  G11B5/09

CPC分类号： G11B20/10009 ,  G11B20/1833 ,  G11B21/083 ,  G11B27/3027 ,  G11B5/5526 ,  G11B5/59655 ,  G11B5/59688 ,  H04L25/4904 ,  G11B2220/20 ,  G11B5/59627 ,  G11B5/5965

摘要： A magnetic disk drive data storage disk defines recording tracks divided into data sectors by narrow servo spokes. A data sector lying between servo spokes is recorded with user data encoded in accordance with a code having a predetermined distance and user data code rate. Each servo spoke of the recording area has at least one servo information field encoded in a wide bi-phase code pattern. The disk drive further includes a synchronous sampling data detection channel having a data transducer head positioned by a servo-controlled actuator over the recording track, a preamplifier for receiving electrical analog signals magnetically induced by the data transducer head from flux transitions present in at least the servo information field, a digital sampler for synchronously sampling the electrical analog signals to produce digital samples, and wide bi-phase decoding circuitry coupled to receive digital samples from the synchronous sampling data detection channel for decoding the wide bi-phase code pattern.

公开(公告)号：US06452990B1

公开(公告)日：2002-09-17

申请号：US09239036

申请日：1999-01-27

申请人： Michael D. Leis ,  Ara Patapoutian ,  Mathew P. Vea ,  Richard M. Ehrlich ,  Kevin D. Fisher ,  James A. Henson ,  William R. Akin, Jr.

发明人： Michael D. Leis ,  Ara Patapoutian ,  Mathew P. Vea ,  Richard M. Ehrlich ,  Kevin D. Fisher ,  James A. Henson ,  William R. Akin, Jr.

IPC分类号： H04L702

CPC分类号： G11B20/10009 ,  G11B5/5526 ,  G11B5/59627 ,  G11B5/5965 ,  G11B5/59655 ,  G11B5/59688 ,  G11B20/1833 ,  G11B21/083 ,  G11B27/3027 ,  G11B2220/20 ,  H04L25/4904

摘要： A magnetic disk drive data storage disk defines recording tracks divided into data sectors by narrow servo spokes. A data sector lying between servo spokes is recorded with user data encoded in accordance with a code having a predetermined distance and user data code rate. Each servo spoke of the recording area has at least one servo information field encoded in a wide bi-phase code pattern. The disk drive further includes a synchronous sampling data detection channel having a data transducer head positioned by a servo-controlled actuator over the recording track, a preamplifier for receiving electrical analog signals magnetically induced by the data transducer head from flux transitions present in at least the servo information field, a digital sampler for synchronously sampling the electrical analog signals to produce digital samples, and wide bi-phase decoding circuitry coupled to receive digital samples from the synchronous sampling data detection channel for decoding the wide bi-phase code pattern.

摘要翻译： 磁盘驱动器数据存储盘通过狭窄的伺服辐条来定义分割成数据扇区的记录轨道。 记录位于伺服轮辐之间的数据扇区，其中用户数据根据具有预定距离的代码和用户数据代码率进行编码。 记录区域的每个伺服轮辐具有编码为宽双相码模式的至少一个伺服信息场。 磁盘驱动器还包括同步采样数据检测通道，其具有由伺服控制致动器在记录轨道上定位的数据传感器头，前置放大器，用于接收由数据传感器头磁场感应的电模拟信号，该电流模拟信号至少存在于 伺服信息字段，用于同步采样电气模拟信号以产生数字样本的数字采样器，以及耦合以从同步采样数据检测通道接收数字样本的宽双相解码电路，用于解码宽双相码模式。

公开(公告)号：US5777760A

公开(公告)日：1998-07-07

申请号：US644810

申请日：1996-05-10

申请人： Nathan J. Hays ,  James A. Henson ,  Christopher M. Carpenter ,  William R. Akin, Jr. ,  Richard M. Ehrlich ,  Lance D. Beazley

发明人： Nathan J. Hays ,  James A. Henson ,  Christopher M. Carpenter ,  William R. Akin, Jr. ,  Richard M. Ehrlich ,  Lance D. Beazley

IPC分类号： G03H1/22 ,  G03H1/26 ,  G03H1/28 ,  G11B7/0065 ,  G11C13/04 ,  G03H1/02 ,  G11B7/24

CPC分类号： G11B7/00781 ,  G03H1/28 ,  G11B7/0065

摘要： A method of holographic recording in a photorefractive medium wherein stored holograms may be retrieved with maximum signal-to noise ratio (SNR) is disclosed. A plurality of servo blocks containing position feedback information is recorded in the crystal and made non-erasable by heating the crystal. The servo blocks are recorded at specific increments, either angular or frequency, depending whether wavelength or angular multiplexing is applied, and each servo block is defined by one of five patterns. Data pages are then recorded at positions or wavelengths enabling each data page to be subsequently reconstructed with servo patterns which provide position feedback information. The method of recording data pages and servo blocks is consistent with conventional practices. In addition, the recording system also includes components (e.g. voice coil motor) which respond to position feedback information and adjust the angular position of the reference angle of a reference beam to maximize SNR by reducing crosstalk, thereby improving storage capacity.

摘要翻译： 公开了一种在光折射介质中的全息记录方法，其中可以以最大信噪比（SNR）来检索存储的全息图。 包含位置反馈信息的多个伺服块被记录在晶体中，并且通过加热晶体使其不可擦除。 根据是否应用波长或角复用，伺服块以特定的增量（角度或频率）进行记录，并且每个伺服块由五种模式之一定义。 然后在位置或波长记录数据页面，使得能够随后使用提供位置反馈信息的伺服模式来重构每个数据页面。 记录数据页和伺服块的方法与传统做法一致。 此外，记录系统还包括响应于位置反馈信息并调整参考光束的参考角度的角位置的组件（例如音圈电机），以通过减少串扰来最大化SNR，从而提高存储容量。

公开(公告)号：US5471176A

公开(公告)日：1995-11-28

申请号：US255162

申请日：1994-06-07

申请人： James A. Henson ,  Scott E. Richmond ,  William R. Akin, Jr.

发明人： James A. Henson ,  Scott E. Richmond ,  William R. Akin, Jr.

IPC分类号： H03K3/02 ,  G06F1/08 ,  H03K3/03 ,  H03K3/78 ,  H03L7/06 ,  H04L7/00 ,  H04L7/033 ,  H03L7/00

CPC分类号： G06F1/08 ,  H03K3/0315 ,  H04L7/0083 ,  H04L7/0337

摘要： A clock generation circuit includes a reference clock for putting out a stable reference clocking signal. A digital ring oscillator includes a series circuit loop having at least one inverting gate and a programmable delay line of plural delays formed a series of tapped digital transmission gates connected between an output and an input of the inverting gate. A multiplexer selects among the series of taps in accordance with a tap selection signal. A clock monitoring circuit is connected to compare the clock output with a stable reference clocking signal to produce a digital clock cycle count. A programmed microcontroller generates the tap selection value as a function of the digital clock cycle count and a desired clock output frequency set point. And, a synchronization circuit synchronizes tap selection value applied to the multiplexer in relation to the present, adjustable clocking signal, and to a logical state of a successor, adjustable clocking signal to be put out by the digital ring oscillator following the tap selection, in order to avoid glitches and without interrupting oscillation.

摘要翻译： 时钟生成电路包括用于输出稳定的参考时钟信号的参考时钟。 数字环形振荡器包括串联电路回路，其具有至少一个反相门和多个延迟的可编程延迟线，形成连接在反相门的输出端和输入端之间的一系列抽头数字传输门。 多路复用器根据抽头选择信号在一系列抽头之间进行选择。 连接时钟监控电路，将时钟输出与稳定的参考时钟信号进行比较，以产生数字时钟周期计数。 编程的微控制器根据数字时钟周期计数和期望的时钟输出频率设定点产生抽头选择值。 并且，同步电路将应用于多路复用器的抽头选择值与当前可调整的时钟信号相同步，并且与随后的数字环形振荡器在抽头选择之后被放出的后继可调时钟信号的逻辑状态同步， 以避免毛刺和不中断振荡。

公开(公告)号：US06178486B1

公开(公告)日：2001-01-23

申请号：US09026472

申请日：1998-02-19

申请人： Parminder Gill ,  Clifford M. Gold ,  James A. Henson

发明人： Parminder Gill ,  Clifford M. Gold ,  James A. Henson

IPC分类号： G06F1200

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0674 ,  G06F13/1642 ,  G06F13/385

摘要： A method and apparatus for arbitrating requests for access to a single buffer memory embedded within a disk drive in which a disk data channel is assigned a highest priority for buffer access within a queue. An arbitration cycle progressively services access requests pending within the queue, beginning with providing buffer access to the disk data channel and following with accesses to other channels during an arbitration cycle completion interval in accordance with a round-robin circular priority arrangement providing orderly access to all channels contending for memory access. At the end of completion interval, buffer access returns to the disk data channel, and thereafter, the arbitration cycle is repeated.

摘要翻译： 一种用于仲裁访问嵌入到磁盘驱动器中的单个缓冲存储器的请求的方法和装置，其中为数据队列中的缓冲器访问分配了最高优先级的磁盘数据通道。 仲裁循环逐渐地服务队列内的访问请求，从提供对磁盘数据通道的缓冲访问开始，并且在仲裁循环完成间隔期间根据循环循环优先级布置对其他通道进行访问，从而提供有序访问所有 争夺内存访问的渠道。 在完成间隔结束时，缓冲器访问返回到磁盘数据通道，此后重复仲裁循环。

公开(公告)号：US6141728A

公开(公告)日：2000-10-31

申请号：US327293

申请日：1999-06-07

申请人： Horia Cristian Simionescu ,  Luan Kha Bui ,  James A. Henson ,  Clifford M. Gold

发明人： Horia Cristian Simionescu ,  Luan Kha Bui ,  James A. Henson ,  Clifford M. Gold

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0866

摘要： A method for managing data blocks in a cache buffer defining date block segments, and for automatically transferring data into and out of the cache buffer. A cache list comprises a plurality of entries each including information identifying a corresponding cache segment, and a set of consecutive data blocks stored in the cache segment. Providing cache status for a requested set of date blocks includes traversing the cache list to locate entries identifying the starting data block in the requested set, and consecutive data blocks successively following the starting data block without interruption, and identifying as a missing data block the first data block in said succession, including said starting data block, not identified in any entry. The missing data block is used to provide status: a full hit if the missing data block is not in the requested set; a miss if the missing data block is the starting data block in the requested set, or a partial hit otherwise. In response to a write command for a new set of data, the cache list is traversed to locate all entries identifying sets of data blocks overlapping the new set. If a located entry identifies a set of data blocks fully overlapping the new set, there is a full hit. If no entry is located, there is miss. Otherwise, there is a partial hit. The new set can be automatically transferred into a predesignated buffer area selected by the cache manager.

摘要翻译： 一种用于管理高速缓冲存储器中的数据块的方法，用于定义日期块段，并用于将数据自动传入和传出高速缓冲存储器。 高速缓存列表包括多个条目，每个条目包括标识对应的高速缓存段的信息和存储在高速缓存段中的一组连续的数据块。 为所请求的一组日期块提供高速缓存状态包括遍历高速缓存列表以定位标识所请求集合中的起始数据块的条目，以及连续地在起始数据块之后不间断的连续数据块，并将第一 所述连续的数据块，包括所述起始数据块，在任何条目中未被识别。 丢失的数据块用于提供状态：如果丢失的数据块不在请求的集合中，则完整命中; 如果丢失的数据块是请求的集合中的起始数据块，否则将导致部分命中。 响应于新的数据集合的写入命令，遍历高速缓存列表以定位识别与新集合重叠的数据块集合的所有条目。 如果所定位的条目标识与新集合完全重叠的一组数据块，则完整命中。 如果没有条目找到，那就是错过。 否则有部分打击。 新集可以自动转移到由缓存管理器选择的预先指定的缓冲区中。

公开(公告)号：US06378051B1

公开(公告)日：2002-04-23

申请号：US09332543

申请日：1999-06-14

申请人： James A. Henson ,  Minnie T. Uppuluri ,  Gregory R. Kahlert

发明人： James A. Henson ,  Minnie T. Uppuluri ,  Gregory R. Kahlert

IPC分类号： G06F1206

CPC分类号： G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0674

摘要： A single microprocessor (22) hard disk drive (10) having a shared buffer memory (40) for storing sector data as well as microprocessor variables and code includes a buffer manager (38) for arbitrating requests from various channels or clients for access to the shared buffer memory. The buffer manager arranges channels including a disk data channel (32, 140), a host interface channel (50, 140), and microprocessor channels (144, 148) into a round-robin circular priority queue, with the disk data channel normally assigned the highest priority for buffer access. A state machine carries out an arbitration cycle by sequentially servicing access requests pending within the queue. The state machine senses (139) a servo interrupt (SVOINT) to elevate the priority of any pending microprocessor access requests to the shared buffer, such that the requests are serviced and cleared rapidly to allow the servo interrupt servicing routine to start sooner. The servo interrupt is preferably asserted during a spoke gate (100) time when a head (16) is sensing a disk (12) servo region (S). During this time data transfers between the disk and the shared buffer memory are stopped, pending buffer memory data transfers can be paused, and head seeking and tracking is controlled. This technique reduces the uncertainty delay in starting the servo interrupt service routine by 10 percent, which restores otherwise lost processing time and reduces head positioner servo (20) phase jitter, thereby improving head tracking and seeking performance.

摘要翻译： 具有用于存储扇区数据的共享缓冲存储器（40）以及微处理器变量和代码的单个微处理器（22）硬盘驱动器（10）包括缓冲器管理器（38），用于仲裁来自各种通道或客户端的访问 共享缓冲存储器。 缓冲器管理器将包括磁盘数据通道（32,140），主机接口通道（50,140）和微处理器通道（144,148）的通道排列成循环循环优先级队列，其中盘数据通道正常地被分配 缓冲区访问的最高优先级。 状态机通过在队列内顺序维护待处理的访问请求来执行仲裁周期。 状态机感测（139）伺服中断（SVOINT）以将任何待处理的微处理器访问请求的优先级提升到共享缓冲器，使得请求被快速清理和清除，以允许伺服中断服务程序更早地启动。 当头（16）感测到盘（12）伺服区（S）时，优选地在轮辐门（100）期间断言伺服中断。 在此期间，磁盘和共享缓冲存储器之间的数据传输停止，暂停缓冲存储器数据传输，并且控制磁头寻找和跟踪。 这种技术将启动伺服中断服务程序的不确定性延迟降低了10％，从而恢复了处理时间，同时降低了磁头定位器伺服（20）的相位抖动，从而提高了磁头跟踪和寻线性能。

公开(公告)号：US5465343A

公开(公告)日：1995-11-07

申请号：US56428

申请日：1993-04-30

申请人： James A. Henson ,  James P. McGrath ,  Bruce R. Peterson ,  Tim R. Glassburn ,  Michael L. Raab ,  James H. Do

发明人： James A. Henson ,  James P. McGrath ,  Bruce R. Peterson ,  Tim R. Glassburn ,  Michael L. Raab ,  James H. Do

IPC分类号： G06F3/06 ,  G06F12/08 ,  G06F13/10 ,  G06F13/12

CPC分类号： G06F3/0601 ,  G06F12/0866 ,  G06F2003/0692 ,  G06F2212/312

摘要： An improved disk drive architecture includes a microcontroller interface circuit connected between a drive microcontroller and a buffer controller. The microcontroller interface circuit includes address mapping registers for mapping at least one predetermined portion of directly addressable memory of the microcontroller to address locations of the drive's cache buffer. The buffer controller circuit includes an access arbitration circuit for arbitrating requests for access to the cache buffer by the drive's data sequencer, the drive's host interface controller and the drive's microcontroller. A microcontroller wait state generator responds to the access arbitration circuit by generating and applying a wait state sequence to the microcontroller until a request it makes for access to the cache buffer can be executed.

摘要翻译： 改进的磁盘驱动器架构包括连接在驱动微控制器和缓冲器控制器之间的微控制器接口电路。 微控制器接口电路包括用于映射微控制器的直接寻址存储器的至少一个预定部分以寻址驱动器的高速缓存缓冲器的位置的地址映射寄存器。 缓冲器控制器电路包括访问仲裁电路，用于通过驱动器的数据定序器，驱动器的主机接口控制器和驱动器的微控制器来仲裁访问高速缓冲存储器的请求。 微控制器等待状态发生器通过产生并将等待状态序列应用于微控制器来响应于访问仲裁电路，直到可以执行其访问高速缓冲存储器的请求。

公开(公告)号：US06760820B2

公开(公告)日：2004-07-06

申请号：US09982646

申请日：2001-10-18

申请人： James A. Henson ,  Minnie T. Uppuluri ,  Gregory R. Kahlert

发明人： James A. Henson ,  Minnie T. Uppuluri ,  Gregory R. Kahlert

IPC分类号： G06F1206

CPC分类号： G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0674

摘要： A single microprocessor (22) hard disk drive (10) having a shared buffer memory (40) for storing sector data as well as microprocessor variables and code includes a buffer manager (38) for arbitrating requests from various channels or clients for access to the shared buffer memory. The buffer manager arranges channels including a disk data channel (32, 140), a host interface channel (50, 140), and microprocessor channels (144, 148) into a round-robin circular priority queue, with the disk data channel normally assigned the highest priority for buffer access. A state machine carries out an arbitration cycle by sequentially servicing access requests pending within the queue. The state machine senses (139) a servo interrupt (SVOINT) to elevate the priority of any pending microprocessor access requests to the shared buffer, such that the requests are serviced and cleared rapidly to allow the servo interrupt servicing routine to start sooner. The servo interrupt is preferably asserted during a spoke gate (100) time when a head (16) is sensing a disk (12) servo region (S). During this time data transfers between the disk and the shared buffer memory are stopped, pending buffer memory data transfers can be paused, and head seeking and tracking is controlled. This technique reduces the uncertainty delay in starting the servo interrupt service routine by 10 percent, which restores otherwise lost processing time and reduces head positioner servo (20) phase jitter, thereby improving head tracking and seeking performance.

摘要翻译： 具有用于存储扇区数据的共享缓冲存储器（40）以及微处理器变量和代码的单个微处理器（22）硬盘驱动器（10）包括缓冲器管理器（38），用于仲裁来自各种通道或客户端的访问 共享缓冲存储器。 缓冲器管理器将包括磁盘数据通道（32,140），主机接口通道（50,140）和微处理器通道（144,148）的通道排列成循环循环优先级队列，其中盘数据通道正常地被分配 缓冲区访问的最高优先级。 状态机通过在队列内顺序维护待处理的访问请求来执行仲裁周期。 状态机感测（139）伺服中断（SVOINT）以将任何待处理的微处理器访问请求的优先级提升到共享缓冲器，使得请求被快速清理和清除，以允许伺服中断服务程序更早地启动。 当头（16）感测到盘（12）伺服区（S）时，优选地在轮辐门（100）期间断言伺服中断。 在此期间，磁盘和共享缓冲存储器之间的数据传输停止，暂停缓冲存储器数据传输，并且控制磁头寻找和跟踪。 这种技术将启动伺服中断服务程序的不确定性延迟降低了10％，从而恢复了处理时间，同时降低了磁头定位器伺服（20）的相位抖动，从而提高了磁头跟踪和寻线性能。