公开(公告)号：US08036042B2

公开(公告)日：2011-10-11

申请号：US12650740

申请日：2009-12-31

申请人： Byung Ryul Kim ,  Duck Ju Kim ,  You Sung Kim ,  Se Chun Park

发明人： Byung Ryul Kim ,  Duck Ju Kim ,  You Sung Kim ,  Se Chun Park

IPC分类号： G11C16/06

CPC分类号： G11C16/3404 ,  G11C16/04

摘要： A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification operation on memory cells included in a first page of a first memory block while raising the program voltage from the first level, storing a level of the program voltage, supplied to the first page when memory cells programmed to have threshold voltages with at least a verification voltage are detected during the verification operation, as a second level, while raising the program voltage from the second level, performing the program operation and the verification operation on each of second to last pages of the first memory block, and after completing the program operation for the first memory block, performing the reset operation for setting the level of the program voltage to the first level.

摘要翻译： 一种操作非易失性存储器件的方法包括执行用于将程序电压的电平设置为第一电平的复位操作，对包括在第一存储块的第一页中的存储器单元执行编程操作和验证操作，同时提高 当在验证操作期间检测到被编程为具有至少具有验证电压的阈值电压的存储单元时，提供给第一页的程序电压电平作为第二电平，同时提高程序 电压从第二电平开始，对第一存储块的第二至第二页中的每一个执行编程操作和验证操作，并且在完成第一存储器块的编程操作之后，执行用于设置程序电平的复位操作 电压到第一级。

公开(公告)号：US08611155B2

公开(公告)日：2013-12-17

申请号：US13341382

申请日：2011-12-30

申请人： Byung Ryul Kim ,  Duck Ju Kim ,  You Sung Kim

发明人： Byung Ryul Kim ,  Duck Ju Kim ,  You Sung Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C16/10

摘要： Programming a semiconductor memory device includes: performing a program loop using a blind program operation until the selected cell threshold voltages reach a first verification level; upon detecting a cell having the threshold voltage reaching the first verification level, verifying whether a cell having the threshold voltage reached a second verification level higher than the first verification level; upon verifying a cell having the threshold voltage reaching the second verification level, continuously performing program loops on cells having the first verification level as a target level and on cells having the second verification level as a target level; and upon verifying no cell having the threshold voltage reaching the second verification level, performing a program loop on memory cells having a target level higher than the first verification level, after programming the memory cells having the first verification level as the target level.

摘要翻译： 编程半导体存储器件包括：使用盲目程序操作执行程序循环，直到所选择的单元阈值电压达到第一验证水平; 一旦检测到阈值电压达到第一验证电平的单元，则验证具有阈值电压的单元是否达到高于第一验证电平的第二验证电平; 在验证具有阈值电压达到第二验证电平的单元的情况下，对具有第一验证电平的单元作为目标电平，以及具有第二验证电平的单元作为目标电平连续执行程序循环; 并且在验证没有阈值电压达到第二验证电平的单元时，在将具有第一验证电平的存储单元编程为目标电平之后，对具有高于第一验证电平的目标电平的存储单元执行程序循环。

公开(公告)号：US07715232B2

公开(公告)日：2010-05-11

申请号：US12138287

申请日：2008-06-12

申请人： Byung Ryul Kim ,  Duck Ju Kim ,  You Sung Kim ,  Sam Kyu Won

发明人： Byung Ryul Kim ,  Duck Ju Kim ,  You Sung Kim ,  Sam Kyu Won

IPC分类号： G11C11/34

CPC分类号： G11C16/26

摘要： In a method of determining a flag state of a non-volatile memory device, an arithmetic logic unit of a microcontroller is employed without an additional circuit. The method includes providing n flag state information about n flag cells, resetting an entire flag state information value, sequentially reading first to n flag state information, increasing the entire flag state information value depending on a read result of the first to n flag state information, and determining a flag state by comparing the entire flag state information value and a critical value.

摘要翻译： 在确定非易失性存储器件的标志状态的方法中，使用微控制器的算术逻辑单元而没有附加电路。 该方法包括提供关于n个标志单元的n个标志状态信息，重置整个标志状态信息值，依次读取n个标志状态信息，根据第一至第n标志状态信息的读取结果增加整个标志状态信息值 并且通过比较整个标志状态信息值和临界值来确定标志状态。

公开(公告)号：US08422309B2

公开(公告)日：2013-04-16

申请号：US12650639

申请日：2009-12-31

申请人： Byung Ryul Kim ,  Duck Ju Kim ,  You Sung Kim ,  Se Chun Park

发明人： Byung Ryul Kim ,  Duck Ju Kim ,  You Sung Kim ,  Se Chun Park

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C5/147 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

摘要： A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit.

摘要翻译： 电压产生电路包括：电压产生控制单元，被配置为响应于选择信号输出具有固定数据值的第一电压电平确定信号和具有变化的数据值的第二电压电平确定信号;以及电压产生单元 被配置为响应于从电压产生控制单元输出的电压电平确定信号产生具有单脉冲形式的电压或具有脉冲形式的电压，其上升沿部分以增量电压步长上升。

公开(公告)号：US08824207B2

公开(公告)日：2014-09-02

申请号：US13601882

申请日：2012-08-31

申请人： Byung Ryul Kim ,  Duck Ju Kim

发明人： Byung Ryul Kim ,  Duck Ju Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3436

摘要： A semiconductor memory device is operated by, inter alia, sequentially inputting program data to page buffers coupled to selected pages of at least four planes in order to program selected memory cells included in the selected pages; performing a program operation on each of the four planes; performing a program verify operation on each of the four planes; and inputting new program data for next pages to the page buffers coupled to the next pages, after determining the selected pages of at least two of the four planes have passed the program verify operation, while performing the program operations and the program verify operations on the two remaining planes.

摘要翻译： 尤其是通过将程序数据顺序地输入到耦合到至少四个平面的选定页面的页缓冲器以便对包括在所选页中的所选择的存储单元进行编程来操作半导体存储器件; 在四个平面中的每一个上执行程序操作; 在四个平面中的每一个上执行程序验证操作; 并且在确定所述四个平面中的至少两个平面中的所选择的页面已经通过了程序验证操作之后，在对所述页面缓冲器执行所述程序操作和所述程序验证操作的同时，将用于下一页的新程序数据输入到耦合到所述下一页的页缓冲器 剩下的两架飞机。

公开(公告)号：US08045393B2

公开(公告)日：2011-10-25

申请号：US12347583

申请日：2008-12-31

申请人： Byung Ryul Kim ,  Jun Seop Chung ,  Duck Ju Kim

发明人： Byung Ryul Kim ,  Jun Seop Chung ,  Duck Ju Kim

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C2216/14

摘要： According to an aspect of a program method of a nonvolatile memory device, a first program operation for programming a first data stored in a first latch may be performed and a cache program signal may be input for inputting a second data to be programmed subsequently. When the cache program signal is input, a determination is made as to whether a first program verify operation is being performed, and if so, the verify operation is stopped, the second data is input, and the first program verify operation is restarted.

摘要翻译： 根据非易失性存储装置的编程方法的一个方面，可以执行用于对存储在第一锁存器中的第一数据进行编程的第一编程操作，并且可以输入高速缓存程序信号，以输入随后要编程的第二数据。 当输入高速缓存程序信号时，确定是否正在执行第一程序验证操作，如果是，则停止验证操作，输入第二数据，并重新启动第一程序验证操作。

公开(公告)号：US08050103B2

公开(公告)日：2011-11-01

申请号：US12361195

申请日：2009-01-28

申请人： You Sung Kim ,  Byung Ryul Kim

发明人： You Sung Kim ,  Byung Ryul Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

摘要： In one aspect of the method of programming a nonvolatile memory device, memory cells selected for a program are determined to belong to a first memory cell group or a second memory cell group based on address information and a program command. According to this determination, to-be-programmed data are input based on information about the number of set data bits, and programming and verification are performed.

摘要翻译： 在非易失性存储器件编程方法的一个方面中，基于地址信息和程序命令，将为程序选择的存储单元确定为属于第一存储单元组或第二存储单元组。 根据该判断，根据关于设定数据位数的信息来输入被编程数据，进行编程和验证。

公开(公告)号：US20090296478A1

公开(公告)日：2009-12-03

申请号：US12361195

申请日：2009-01-28

申请人： You Sung KIM ,  Byung Ryul Kim

发明人： You Sung KIM ,  Byung Ryul Kim

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

摘要： In one aspect of the method of programming a nonvolatile memory device, memory cells selected for a program are determined to belong to a first memory cell group or a second memory cell group based on address information and a program command. According to this determination, to-be-programmed data are input based on information about the number of set data bits, and programming and verification are performed.

摘要翻译： 在非易失性存储器件编程方法的一个方面中，基于地址信息和程序命令，将为程序选择的存储单元确定为属于第一存储单元组或第二存储单元组。 根据该判断，根据关于设定数据位数的信息来输入被编程数据，进行编程和验证。

公开(公告)号：US20090031080A1

公开(公告)日：2009-01-29

申请号：US11950303

申请日：2007-12-04

申请人： You Sung Kim ,  Byung Ryul Kim

发明人： You Sung Kim ,  Byung Ryul Kim

IPC分类号： G06F12/00

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： A flash memory device includes a memory cell array, a peri circuit unit, an I/O controller, and a controller. The memory cell array includes a plurality of memory cells respectively connected to a plurality of bit line pairs and a plurality word lines. The peri circuit unit is configured to program data into the memory cell array or read data stored in the memory cell array in response to a command input through a control bus. The I/O controller is configured to receive data for programming and supply the data to the peri circuit unit in response to a command provided through a data input/output (I/O) bus. The controller is configured to control the I/O controller to perform a voltage setup operation for a program while the data for program is received.

摘要翻译： 闪存器件包括存储单元阵列，周边电路单元，I / O控制器和控制器。 存储单元阵列包括分别连接到多个位线对和多个字线的多个存储单元。 周边电路单元被配置为响应于通过控制总线输入的命令，将数据编程到存储单元阵列中或读取存储在存储单元阵列中的数据。 I / O控制器被配置为接收用于编程的数据，并响应于通过数据输入/输出（I / O）总线提供的命令将数据提供给周边电路单元。 控制器被配置为控制I / O控制器，以便在接收到用于节目的数据时对节目执行电压设置操作。

公开(公告)号：US07567450B2

公开(公告)日：2009-07-28

申请号：US11618493

申请日：2006-12-29

申请人： Byung Ryul Kim

发明人： Byung Ryul Kim

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C7/02

CPC分类号： G11C17/12

摘要： A low power ROM includes a plurality of ROM core groups coupled between a plurality of word lines and bit lines, a word line decoder for selecting a desired word line of the plurality of word lines, a column decoder for selecting a desired bit line of the plurality of bit lines, a common reference voltage generator for generating a common reference voltage, and a plurality of sense amplifiers having the same number as the number of ROM core groups, for comparing an output of the common reference voltage generator and data of a bit line of each ROM core group.

摘要翻译： 低功率ROM包括耦合在多个字线和位线之间的多个ROM核心组，用于选择多个字线的期望字线的字线解码器，用于选择所述多个字线的所需位线的列解码器 多个位线，用于产生公共参考电压的公共参考电压发生器和具有与ROM核心组数相同数量的多个读出放大器，用于比较公共参考电压发生器的输出和位的数据 每个ROM核心组的行。