公开(公告)号：US20060274574A1

公开(公告)日：2006-12-07

申请号：US11502563

申请日：2006-08-11

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US20050195633A1

公开(公告)日：2005-09-08

申请号：US11070196

申请日：2005-03-03

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

IPC分类号： G11C13/02 ,  G11C13/00 ,  G11C16/02 ,  G11C16/10 ,  G11C19/08 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2013/0092

摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

摘要翻译： 一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻 状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。 在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。 施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。 设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

公开(公告)号：US07110286B2

公开(公告)日：2006-09-19

申请号：US10919371

申请日：2004-08-17

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US07502251B2

公开(公告)日：2009-03-10

申请号：US11502563

申请日：2006-08-11

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

摘要翻译： 相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。 相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。 地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程 电路进入结晶状态。 写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变至少一个复位和设置的脉冲电流的脉冲宽度和脉冲计数中的至少一个。

公开(公告)号：US07274586B2

公开(公告)日：2007-09-25

申请号：US11070196

申请日：2005-03-03

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2013/0092

摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

摘要翻译： 一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻 状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。 在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。 施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。 设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

公开(公告)号：US20050169093A1

公开(公告)日：2005-08-04

申请号：US10919371

申请日：2004-08-17

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C13/02 ,  G11C8/00 ,  G11C16/02

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

摘要翻译： 相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。 相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。 地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程 电路进入结晶状态。 写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变复位和设置脉冲电流中的至少一个的脉冲宽度和脉冲计数中的至少一个。

公开(公告)号：US07994493B2

公开(公告)日：2011-08-09

申请号：US12196137

申请日：2008-08-21

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L29/04 ,  H01L47/00

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.

摘要翻译： 相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。 字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。 第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。 多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

公开(公告)号：US20060250885A1

公开(公告)日：2006-11-09

申请号：US11483477

申请日：2006-07-10

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-Keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C8/00

CPC分类号： G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

摘要： A firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation are described. The phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block. The driving unit applies a firing current to the memory cell array blocks in response to the firing mode signal. According to the phase change memory device and the initial firing method, the time taken to perform the initial firing operation can be reduced. In addition, since the numbers of the needed signals are minimized, a large number of chips on a single wafer can be simultaneously tested.

摘要翻译： 描述能够有效地执行点火操作的相变存储器件和相变存储器的点火方法。 相变存储器件包括多个存储单元阵列块，计数器时钟生成单元，解码单元和驱动单元。 每个存储单元阵列块具有相变存储单元。 计数器时钟产生单元响应于外部时钟信号和触发模式信号输出第一至第三计数器时钟信号，其中第一至第三计数器时钟信号具有不同的周期。 解码单元响应于第一至第三计数器时钟信号输出选择多个存储单元阵列块中的一个的块地址，使得能够选择的存储单元阵列块的字线的字线地址和冗余字 行地址，其使能所选存储单元阵列块的冗余字线。 驱动单元响应于点火模式信号向存储单元阵列块施加点火电流。 根据相变存储器件和初始烧制方法，可以减少执行初始点火操作所花费的时间。 此外，由于所需信号的数量最小化，可以同时测试单个晶片上的大量芯片。

公开(公告)号：US20060186483A1

公开(公告)日：2006-08-24

申请号：US11324112

申请日：2005-12-30

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L29/76

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

公开(公告)号：US20080303016A1

公开(公告)日：2008-12-11

申请号：US12196137

申请日：2008-08-21

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L45/00

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。