公开(公告)号：US08139432B2

公开(公告)日：2012-03-20

申请号：US12901168

申请日：2010-10-08

申请人： Byung-gil Choi ,  Beak-hyung Cho ,  Jun-Soo Bae ,  Kwang-Jin Lee

发明人： Byung-gil Choi ,  Beak-hyung Cho ,  Jun-Soo Bae ,  Kwang-Jin Lee

IPC分类号： G11C7/04

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C8/12 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2029/2602 ,  H01L27/24

摘要： A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

摘要翻译： 一种非易失性存储器件，包括：多个存储体，每个存储体各自独立地操作并且包括多个电阻存储器单元，每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件; 多个全局位线，每个全局位线由多个存储体共享; 包括一个或多个参考单元的温度补偿电路; 以及数据读取电路，其电连接到所述多个全局位线，并且通过向所述电阻存储单元中的至少一个提供根据所述参考单元的电阻而变化的电流来执行读取操作。

公开(公告)号：US20110026303A1

公开(公告)日：2011-02-03

申请号：US12901168

申请日：2010-10-08

申请人： Byung-Gil Choi ,  Beak-hyung Cho ,  Jun Soo Bae ,  Kwang-Jin Lee

发明人： Byung-Gil Choi ,  Beak-hyung Cho ,  Jun Soo Bae ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C8/12 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2029/2602 ,  H01L27/24

摘要： A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

摘要翻译： 一种非易失性存储器件，包括：多个存储体，每个存储体各自独立地操作并且包括多个电阻存储器单元，每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件; 多个全局位线，每个全局位线由多个存储体共享; 包括一个或多个参考单元的温度补偿电路; 以及数据读取电路，其电连接到所述多个全局位线，并且通过向所述电阻存储器单元中的至少一个提供根据所述参考单元的电阻而变化的电流来执行读取操作。

公开(公告)号：US08050084B2

公开(公告)日：2011-11-01

申请号：US12893413

申请日：2010-09-29

申请人： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho

发明人： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/12 ,  G11C7/04 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5634

摘要： A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.

摘要翻译： 非易失性存储器件包括存储单元阵列，其包括多个非易失性存储单元，每个非易失性存储单元具有对应于多个第一电阻分布之一的电阻，温度补偿电路包括一个或多个参考单元，每个参考单元具有对应于一个 或更多的第二电阻分布，以及包括补偿单元和读出放大器的数据读取电路，所述补偿单元适于向感测节点提供补偿电流，所述补偿电流的量基于每个参考单元的电阻而变化， 并且所述读出放大器适于将感测节点的电平与参考电平进行比较并输出比较结果。

公开(公告)号：US08134866B2

公开(公告)日：2012-03-13

申请号：US12652842

申请日：2010-01-06

申请人： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

发明人： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

摘要： A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

摘要翻译： 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。

公开(公告)号：US20110080775A1

公开(公告)日：2011-04-07

申请号：US12893413

申请日：2010-09-29

申请人： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho

发明人： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho

IPC分类号： G11C11/00 ,  G11C7/04

CPC分类号： G11C8/12 ,  G11C7/04 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5634

摘要： A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.

摘要翻译： 非易失性存储器件包括存储单元阵列，其包括多个非易失性存储单元，每个非易失性存储单元具有对应于多个第一电阻分布之一的电阻，温度补偿电路包括一个或多个参考单元，每个参考单元具有对应于一个 或更多的第二电阻分布，以及包括补偿单元和读出放大器的数据读取电路，所述补偿单元适于向感测节点提供补偿电流，所述补偿电流的量基于每个参考单元的电阻而变化， 并且所述读出放大器适于将感测节点的电平与参考电平进行比较并输出比较结果。

公开(公告)号：US07751232B2

公开(公告)日：2010-07-06

申请号：US11953146

申请日：2007-12-10

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US20070133269A1

公开(公告)日：2007-06-14

申请号：US11488010

申请日：2006-07-18

申请人： Kwang-Jin Lee ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Kwang-Jin Lee ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C13/0059 ,  G11C17/16 ,  G11C17/165

摘要： In one aspect, a non-volatile memory includes a phase-change memory cell array which includes a plurality of normal phase-change memory cells and a plurality of pseudo one-time-programmable (OTP) phase-change memory cells, a write driver which writes data into the normal and pseudo OTP phase-change memory cells of the phase-change memory cell array, and an OTP controller which selectively disables the write driver.

摘要翻译： 一方面，非易失性存储器包括相变存储单元阵列，其包括多个正常相变存储器单元和多个伪一次可编程（OTP）相变存储器单元，写入驱动器 其将数据写入相变存储单元阵列的正常和伪OTP相变存储单元，以及选择性地禁用写入驱动器的OTP控制器。

公开(公告)号：US07869271B2

公开(公告)日：2011-01-11

申请号：US12787571

申请日：2010-05-26

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US20080101131A1

公开(公告)日：2008-05-01

申请号：US11790146

申请日：2007-04-24

申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

IPC分类号： G11C7/06

CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

公开(公告)号：US07542356B2

公开(公告)日：2009-06-02

申请号：US11790146

申请日：2007-04-24

申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

IPC分类号： G11C7/06

CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。