公开(公告)号：US20110026303A1

公开(公告)日：2011-02-03

申请号：US12901168

申请日：2010-10-08

申请人： Byung-Gil Choi ,  Beak-hyung Cho ,  Jun Soo Bae ,  Kwang-Jin Lee

发明人： Byung-Gil Choi ,  Beak-hyung Cho ,  Jun Soo Bae ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C8/12 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2029/2602 ,  H01L27/24

摘要： A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

摘要翻译： 一种非易失性存储器件，包括：多个存储体，每个存储体各自独立地操作并且包括多个电阻存储器单元，每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件; 多个全局位线，每个全局位线由多个存储体共享; 包括一个或多个参考单元的温度补偿电路; 以及数据读取电路，其电连接到所述多个全局位线，并且通过向所述电阻存储器单元中的至少一个提供根据所述参考单元的电阻而变化的电流来执行读取操作。

公开(公告)号：US08139432B2

公开(公告)日：2012-03-20

申请号：US12901168

申请日：2010-10-08

申请人： Byung-gil Choi ,  Beak-hyung Cho ,  Jun-Soo Bae ,  Kwang-Jin Lee

发明人： Byung-gil Choi ,  Beak-hyung Cho ,  Jun-Soo Bae ,  Kwang-Jin Lee

IPC分类号： G11C7/04

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C8/12 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2029/2602 ,  H01L27/24

摘要： A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

摘要翻译： 一种非易失性存储器件，包括：多个存储体，每个存储体各自独立地操作并且包括多个电阻存储器单元，每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件; 多个全局位线，每个全局位线由多个存储体共享; 包括一个或多个参考单元的温度补偿电路; 以及数据读取电路，其电连接到所述多个全局位线，并且通过向所述电阻存储单元中的至少一个提供根据所述参考单元的电阻而变化的电流来执行读取操作。

公开(公告)号：US08243495B2

公开(公告)日：2012-08-14

申请号：US12379399

申请日：2009-02-20

申请人： Byung-gil Choi ,  Won-ryul Chung ,  Beak-hyung Cho

发明人： Byung-gil Choi ,  Won-ryul Chung ,  Beak-hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C2213/72

摘要： A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed. The semiconductor memory device or PRAM may further include jump contacts for connecting the plurality of cut sub-word lines. In a PRAM device including the plurality of main word lines and the plurality of sub-word lines being in different layers, the number of jump contacts for connecting the plurality of main word lines to a transistor of a sub-word line decoder is the same in each sub-word line or the plurality of main word lines are bent several times so that a parasitic resistance on a word line and power consumption may be reduced, and a sensing margin may be increased.

摘要翻译： 能够降低字线的电阻的相变随机存取存储器（PRAM）装置可以包括半导体存储器件的多个主字线或在与多个 子字线被排列。 半导体存储器件或PRAM还可以包括用于连接多个切割子字线的跳跃触点。 在包括多个主字线和多个子字线在不同层中的PRAM装置中，用于将多个主字线连接到子字线解码器的晶体管的跳转触点的数量是相同的 在每个子字线或多个主字线被多次弯曲，从而可以减少字线上的寄生电阻和功耗，并且可以增加感测裕度。

公开(公告)号：US20080158941A1

公开(公告)日：2008-07-03

申请号：US12003442

申请日：2007-12-26

申请人： Byung-gil Choi ,  Beak-hyung Cho

发明人： Byung-gil Choi ,  Beak-hyung Cho

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/18 ,  G11C13/0004 ,  G11C2029/2602 ,  H01L27/24

摘要： The nonvolatile memory device includes a plurality of memory banks, each of which includes a plurality of nonvolatile memory cells. Each cell includes a variable resistive element having a resistance varying depending on stored data. A plurality of global bit lines are included, and each global bit line is shared by the plurality of memory banks. A plurality of main word lines are arranged corresponding to one of the plurality of memory banks.

摘要翻译： 非易失性存储器件包括多个存储体，每个存储体包括多个非易失性存储单元。 每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件。 包括多个全局位线，并且每个全局位线被多个存储体共享。 多个主字线被布置成与多个存储体之一相对应。

公开(公告)号：US07929337B2

公开(公告)日：2011-04-19

申请号：US12379398

申请日：2009-02-20

申请人： Byung-gil Choi ,  Beak-hyung Cho

发明人： Byung-gil Choi ,  Beak-hyung Cho

IPC分类号： G11C11/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10

CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C2207/002 ,  G11C2216/22

摘要： A semiconductor memory device includes at least one write global bit line connected to a plurality of local bit lines and at least one read global bit line connected to the local bit lines. The phase-change memory device having the write global bit line and the read global bit line suppress coupling noise generated during a read-while-write operation.

摘要翻译： 半导体存储器件包括连接到多个局部位线的至少一个写入全局位线和连接到局部位线的至少一个读取全局位线。 具有写入全局位线和读取的全局位线的相变存储器件抑制在读写操作期间产生的耦合噪声。

公开(公告)号：US07821865B2

公开(公告)日：2010-10-26

申请号：US12003442

申请日：2007-12-26

申请人： Byung-gil Choi ,  Beak-hyung Cho

发明人： Byung-gil Choi ,  Beak-hyung Cho

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C13/0004 ,  G11C2029/2602 ,  H01L27/24

摘要： The nonvolatile memory device includes a plurality of memory banks, each of which includes a plurality of nonvolatile memory cells. Each cell includes a variable resistive element having a resistance varying depending on stored data. A plurality of global bit lines are included, and each global bit line is shared by the plurality of memory banks. A plurality of main word lines are arranged corresponding to one of the plurality of memory banks.

摘要翻译： 非易失性存储器件包括多个存储体，每个存储体包括多个非易失性存储单元。 每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件。 包括多个全局位线，并且每个全局位线被多个存储体共享。 多个主字线被布置成与多个存储体之一相对应。

公开(公告)号：US20090213647A1

公开(公告)日：2009-08-27

申请号：US12379399

申请日：2009-02-20

申请人： Byung-gil Choi ,  Won-ryul Chung ,  Beak-hyung Cho

发明人： Byung-gil Choi ,  Won-ryul Chung ,  Beak-hyung Cho

IPC分类号： G11C11/00 ,  G11C8/10

CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C2213/72

摘要： A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed. The semiconductor memory device or PRAM may further include jump contacts for connecting the plurality of cut sub-word lines. In a PRAM device including the plurality of main word lines and the plurality of sub-word lines being in different layers, the number of jump contacts for connecting the plurality of main word lines to a transistor of a sub-word line decoder is the same in each sub-word line or the plurality of main word lines are bent several times so that a parasitic resistance on a word line and power consumption may be reduced, and a sensing margin may be increased.

摘要翻译： 能够降低字线的电阻的相变随机存取存储器（PRAM）装置可以包括半导体存储器件的多个主字线或在与多个 子字线被排列。 半导体存储器件或PRAM还可以包括用于连接多个切割子字线的跳跃触点。 在包括多个主字线和多个子字线在不同层中的PRAM装置中，用于将多个主字线连接到子字线解码器的晶体管的跳转触点的数量是相同的 在每个子字线或多个主字线被多次弯曲，从而可以减少字线上的寄生电阻和功耗，并且可以增加感测裕度。

公开(公告)号：US20080062741A1

公开(公告)日：2008-03-13

申请号：US11898125

申请日：2007-09-10

申请人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

发明人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

IPC分类号： G11C29/44

CPC分类号： G11C13/0004 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

摘要： Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.

摘要翻译： 提供了一种测试相变随机存取存储器（PRAM）的方法。 该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线， 所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压 线。

公开(公告)号：US20070153616A1

公开(公告)日：2007-07-05

申请号：US11640956

申请日：2006-12-19

申请人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

发明人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.

摘要翻译： 提供了相变存储器件。 相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第 多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及 行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

公开(公告)号：US20050068804A1

公开(公告)日：2005-03-31

申请号：US10937943

申请日：2004-09-11

申请人： Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Beak-hyung Cho

发明人： Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Beak-hyung Cho

IPC分类号： G11C13/00 ,  G11C13/02 ,  G11C16/02 ,  G11C16/34 ,  H01L27/105 ,  H01L45/00 ,  G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0064 ,  G11C13/0069

摘要： Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a reset state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.

摘要翻译： 提供了一种相变存储器件和方法，其将相变材料的电阻保持在恒定电阻范围内的复位状态。 在该方法中，将数据提供给第一相变存储器单元，然后首先确定存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据是否相同。 如果存储在第一相变存储器单元中的数据和提供给第一相变存储单元的数据不相同，则向第一相变存储单元提供互补写入电流，并且第二确定数据 存储在第一相变存储单元中，提供给第一相变存储单元的数据相同。 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据相同，则将数据提供给第二相变存储单元。