公开(公告)号：US20090267137A1

公开(公告)日：2009-10-29

申请号：US12498615

申请日：2009-07-07

申请人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

发明人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

IPC分类号： H01L29/792

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

摘要翻译： 提供一种制造半导体器件的方法，通过该方法，形成在半导体衬底的单元阵列区域上的单元晶体管采用其中使用间隔物形状的电极形成栅极并且多位操作是 可能使用局部位，并且可以在作为半导体衬底的剩余区域的外围电路区域上形成具有根据晶体管的功能而被优化以满足不同要求的结构的晶体管。 在该方法中，在单元阵列区域上形成单元晶体管。 单元晶体管包括陷波门结构，在陷波栅结构下形成在半导体衬底上的第一沟道区，形成在第一沟道区的两侧的源区和漏区，形成在第一沟道区之间的第一栅极绝缘膜 沟道区域和陷波门结构，以及局部地形成在与第一沟道区和陷波栅结构之间的源极和漏极区相邻的区域上的存储层。 在形成单元晶体管的同时，在外围电路区域上形成有包含至少一个具有与单元晶体管不同的结构的晶体管的多个外围电路晶体管。

公开(公告)号：US08044451B2

公开(公告)日：2011-10-25

申请号：US12498615

申请日：2009-07-07

申请人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

发明人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

IPC分类号： H01L29/788

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

摘要翻译： 提供一种制造半导体器件的方法，通过该方法，形成在半导体衬底的单元阵列区域上的单元晶体管采用其中使用间隔物形状的电极形成栅极并且多位操作是 可能使用局部位，并且可以在作为半导体衬底的剩余区域的外围电路区域上形成具有根据晶体管的功能而被优化以满足不同要求的结构的晶体管。 在该方法中，在单元阵列区域上形成单元晶体管。 单元晶体管包括陷波门结构，在陷波栅结构下形成在半导体衬底上的第一沟道区，形成在第一沟道区的两侧的源区和漏区，形成在第一沟道区之间的第一栅极绝缘膜 沟道区域和陷波门结构，以及局部地形成在与第一沟道区和陷波栅结构之间的源极和漏极区相邻的区域上的存储层。 在形成单元晶体管的同时，在外围电路区域上形成有包含至少一个具有与单元晶体管不同的结构的晶体管的多个外围电路晶体管。

公开(公告)号：US20060154421A1

公开(公告)日：2006-07-13

申请号：US11329943

申请日：2006-01-11

申请人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

发明人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed .on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

摘要翻译： 提供一种制造半导体器件的方法，通过该半导体器件，在半导体衬底的单元阵列区域中形成的单元晶体管采用其中使用间隔物形状的电极形成栅极和多位操作的结构 可以使用局部位，并且可以在作为半导体衬底的剩余区域的外围电路区域上形成具有根据晶体管的功能而优化以满足不同要求的结构的晶体管。 在该方法中，在单元阵列区域上形成单元晶体管。 单元晶体管包括陷波门结构，在陷波栅结构下形成在半导体衬底上的第一沟道区，形成在第一沟道区的两侧的源区和漏区，形成在第一沟道区之间的第一栅极绝缘膜 沟道区域和陷波门结构，以及局部地形成在与第一沟道区和陷波栅结构之间的源极和漏极区相邻的区域上的存储层。 在形成单元晶体管的同时，在外围电路区域上形成有包含至少一个具有与单元晶体管不同的结构的晶体管的多个外围电路晶体管。

公开(公告)号：US20080283879A1

公开(公告)日：2008-11-20

申请号：US12182593

申请日：2008-07-30

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

IPC分类号： H01L29/00

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

摘要翻译： 提供具有部分厚度差的栅极介电层的晶体管及其制造方法。 该方法包括形成具有形成在半导体衬底上的较薄厚度的主要部分的栅介质层，以及形成在主体两侧的较厚厚度的侧壁部分。 第一栅极形成为与栅介质层的主要部分重叠，并形成覆盖栅介质层的侧壁部分并覆盖第一栅极的第二栅极层。 蚀刻第二栅极层，从而形成在第一栅极的侧壁上以间隔物形状图案化的第二栅极。 使用第二栅极作为掩模来选择性地蚀刻栅极电介质层的暴露的侧壁部分，从而形成与第二栅极对准的栅极电介质层的图案。 在由第二栅极暴露的半导体衬底的一部分中形成源极/漏极。

公开(公告)号：US20050269629A1

公开(公告)日：2005-12-08

申请号：US11084922

申请日：2005-03-21

申请人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

发明人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L21/26513 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/78624

摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

摘要翻译： 翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。 翅片在基底上并沿着和垂直方向横向延伸。 栅电极覆盖翅片的一侧和顶部。 栅绝缘层位于栅电极和鳍之间。 翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。 翅片的源极区域具有与鳍片的漏极区域不同的宽度。

公开(公告)号：US07652322B2

公开(公告)日：2010-01-26

申请号：US12014262

申请日：2008-01-15

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

摘要翻译： 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

公开(公告)号：US20060154410A1

公开(公告)日：2006-07-13

申请号：US11329623

申请日：2006-01-11

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

IPC分类号： H01L21/338 ,  H01L21/425

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

摘要翻译： 提供具有部分厚度差的栅极介电层的晶体管及其制造方法。 该方法包括形成具有形成在半导体衬底上的较薄厚度的主要部分的栅介质层，以及形成在主体两侧的较厚厚度的侧壁部分。 第一栅极形成为与栅介质层的主要部分重叠，并形成覆盖栅介质层的侧壁部分并覆盖第一栅极的第二栅极层。 蚀刻第二栅极层，从而形成在第一栅极的侧壁上以间隔物形状图案化的第二栅极。 使用第二栅极作为掩模来选择性地蚀刻栅极电介质层的暴露的侧壁部分，从而形成与第二栅极对准的栅极电介质层的图案。 在由第二栅极暴露的半导体衬底的一部分中形成源极/漏极。

公开(公告)号：US20080111180A1

公开(公告)日：2008-05-15

申请号：US12014262

申请日：2008-01-15

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

摘要翻译： 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

公开(公告)号：US07332386B2

公开(公告)日：2008-02-19

申请号：US11084922

申请日：2005-03-21

申请人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

发明人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/26513 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/78624

摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

摘要翻译： 翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。 翅片在基底上并沿着和垂直方向横向延伸。 栅电极覆盖翅片的一侧和顶部。 栅绝缘层位于栅电极和鳍之间。 翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。 翅片的源极区域具有与鳍片的漏极区域不同的宽度。

公开(公告)号：US07419879B2

公开(公告)日：2008-09-02

申请号：US11329623

申请日：2006-01-11

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

摘要翻译： 提供具有部分厚度差的栅极介电层的晶体管及其制造方法。 该方法包括形成具有形成在半导体衬底上的较薄厚度的主要部分的栅介质层，以及形成在主体两侧的较厚厚度的侧壁部分。 第一栅极形成为与栅介质层的主要部分重叠，并形成覆盖栅介质层的侧壁部分并覆盖第一栅极的第二栅极层。 蚀刻第二栅极层，从而形成在第一栅极的侧壁上以间隔物形状图案化的第二栅极。 使用第二栅极作为掩模来选择性地蚀刻栅极电介质层的暴露的侧壁部分，从而形成与第二栅极对准的栅极电介质层的图案。 在由第二栅极暴露的半导体衬底的一部分中形成源极/漏极。